?? mode7cnt.sprj
字號:
`timescale 1ns/1ns
`include "fdq.vf"
`include "and4or2.vf"
`include "and5or2.vf"
`include "mode7cnt.vf"
`include "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
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