// Verilog model created from schematic andnor2_p.sch - Wed Nov 13 16:47:40 2002


`timescale 1ns / 1ps

module andnor2_p(in1, in2, in3, in4, in5, out_t);

 input in1;
 input in2;
 input in3;
 input in4;
 input in5;
output out_t;

wire XLXN_1;
wire XLXN_2;

AND2 XLXI_1 (.I0(in2), .I1(in1), .O(XLXN_1));
AND3 XLXI_4 (.I0(in5), .I1(in4), .I2(in3), .O(XLXN_2));
NOR2 XLXI_3 (.I0(XLXN_2), .I1(XLXN_1), .O(out_t));
endmodule