# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : View Verilog Functional Model
andnor2.vf
# Schematic : View Verilog Functional Model
andnor2_p.vf
# Check Syntax
andnor2_p.stx
# Schematic : View Verilog Functional Model
fdq.vf
# Check Syntax
fdq.stx
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : View Verilog Functional Model
andnor2.vf
# Check Syntax
andnor2.stx
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : View Verilog Functional Model
mode7cnt.vf
# Check Syntax
mode7cnt.stx
# xst flow : RunXST
mode7cnt.syr
mode7cnt.ngr
mode7cnt.prj
mode7cnt.sprj
mode7cnt.ana
mode7cnt.stx
mode7cnt.cmd_log
mode7cnt.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
j:\projects\ise\mod7cnt/_ngo
mode7cnt.ngd
mode7cnt_ngdbuild.nav
mode7cnt.bld
.untf
mode7cnt.cmd_log
# Implementation : Map
mode7cnt.nc1
mode7cnt.mrp
mode7cnt.pcf
mode7cnt.ngm
mode7cnt_map.ngm
mode7cnt.mdf
mode7cnt_map.ncd
__projnav/map.log
mode7cnt.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mode7cnt.twr
mode7cnt.twx
mode7cnt.tsi
mode7cnt.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
mode7cnt.ncd
mode7cnt.par
mode7cnt.pad
mode7cnt.dly
mode7cnt.xpi
mode7cnt.grf
mode7cnt.itr
mode7cnt_last_par.ncd
__projnav/par.log
mode7cnt.cmd_log
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : View Verilog Functional Model
and5or2.vf
# Schematic : View Verilog Functional Model
and4or2.vf
# Check Syntax
and4or2.stx
# Schematic : View Verilog Functional Model
and5or2.vf
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : View Verilog Functional Model
and5or2.vf
# Check Syntax
and5or2.stx
# Schematic : PDCL (jhdparse)
# Check Syntax
fdq.stx
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : PDCL (jhdparse)
# Schematic : View Verilog Functional Model
mode7cnt.vf
# Check Syntax
mode7cnt.stx
mode7cnt.ngc
# xst flow : RunXST
mode7cnt.syr
mode7cnt.ngr
mode7cnt.prj
mode7cnt.sprj
mode7cnt.ana
mode7cnt.stx
mode7cnt.cmd_log
mode7cnt.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
j:\projects\ise\mod7cnt/_ngo
mode7cnt.ngd
mode7cnt_ngdbuild.nav
mode7cnt.bld
.untf
mode7cnt.cmd_log
# Implementation : Map
mode7cnt.nc1
mode7cnt.mrp
mode7cnt.pcf
mode7cnt.ngm
mode7cnt_map.ngm
mode7cnt.mdf
mode7cnt_map.ncd
__projnav/map.log
mode7cnt.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mode7cnt.twr
mode7cnt.twx
mode7cnt.tsi
mode7cnt.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
mode7cnt.ncd
mode7cnt.par
mode7cnt.pad
mode7cnt.dly
mode7cnt.xpi
mode7cnt.grf
mode7cnt.itr
mode7cnt_last_par.ncd
__projnav/par.log
mode7cnt.cmd_log
# Generate Programming File
__projnav/mode7cnt_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
mode7cnt.ut
# Generate Programming File
mode7cnt.bgn
mode7cnt.rbt
mode7cnt.ll
mode7cnt.msk
mode7cnt.drc
mode7cnt.nky
mode7cnt.bit
mode7cnt.bin
mode7cnt.isc
mode7cnt.cmd_log
# f2g Migration
_impact.cmd
_impact.log
mode7cnt.ngr
# Schematic : PDCL (jhdparse)
__projnav/and4or2_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/and5or2_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/mode7cnt_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/fdq_jhdparse_tcl.rsp
# Schematic : View Verilog Functional Model
mode7cnt.vf
# Schematic : View Verilog Functional Model
fdq.vf
# Schematic : View Verilog Functional Model
and4or2.vf
# Schematic : View Verilog Functional Model
and5or2.vf
# XST (Creating Lso File) : 
mode7cnt.lso
# xst flow : RunXST
mode7cnt.syr
mode7cnt.prj
mode7cnt.sprj
mode7cnt.ana
mode7cnt.stx
mode7cnt.cmd_log
mode7cnt.ngc
mode7cnt.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\workstation\ise第二版2004-05-13\cd\example-2-3\ecs_demo\mod7cnt/_ngo
mode7cnt.ngd
mode7cnt_ngdbuild.nav
mode7cnt.bld
.untf
mode7cnt.cmd_log
# Implementation : Map
mode7cnt_map.ncd
mode7cnt.ngm
mode7cnt.pcf
mode7cnt.nc1
mode7cnt.mrp
mode7cnt_map.mrp
mode7cnt.mdf
__projnav/map.log
mode7cnt.cmd_log
MAP_NO_GUIDE_FILE_CPF "mode7cnt"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mode7cnt.twr
mode7cnt.twx
mode7cnt.tsi
mode7cnt.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
mode7cnt.ncd
mode7cnt.par
mode7cnt.pad
mode7cnt_pad.txt
mode7cnt_pad.csv
mode7cnt.pad_txt
mode7cnt.dly
reportgen.log
mode7cnt.xpi
mode7cnt.grf
mode7cnt.itr
mode7cnt_last_par.ncd
__projnav/par.log
mode7cnt.placed_ncd_tracker
mode7cnt.routed_ncd_tracker
mode7cnt.cmd_log
PAR_NO_GUIDE_FILE_CPF "mode7cnt"
# Generate Programming File
__projnav/mode7cnt_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
mode7cnt.ut
# Generate Programming File
mode7cnt.bgn
mode7cnt.rbt
mode7cnt.ll
mode7cnt.msk
mode7cnt.drc
mode7cnt.nky
mode7cnt.bit
mode7cnt.bin
mode7cnt.isc
mode7cnt.cmd_log