[COREGEN.VHDL Component Instantiation.dpram_core]
type=template
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component dpram_core"
text005="    port ("
text006="    addra: IN std_logic_VECTOR(3 downto 0);"
text007="    addrb: IN std_logic_VECTOR(3 downto 0);"
text008="    clka: IN std_logic;"
text009="    clkb: IN std_logic;"
text010="    dina: IN std_logic_VECTOR(15 downto 0);"
text011="    dinb: IN std_logic_VECTOR(15 downto 0);"
text012="    douta: OUT std_logic_VECTOR(15 downto 0);"
text013="    doutb: OUT std_logic_VECTOR(15 downto 0);"
text014="    wea: IN std_logic;"
text015="    web: IN std_logic);"
text016="end component;"
text017=""
text018=""
text019=""
text020=""
text021=" "
text022="-------------------------------------------------------------"
text023=" "
text024="-- The following code must appear in the VHDL architecture body."
text025="-- Substitute your own instance name and net names."
text026=" "
text027="your_instance_name : dpram_core"
text028="        port map ("
text029="            addra => addra,"
text030="            addrb => addrb,"
text031="            clka => clka,"
text032="            clkb => clkb,"
text033="            dina => dina,"
text034="            dinb => dinb,"
text035="            douta => douta,"
text036="            doutb => doutb,"
text037="            wea => wea,"
text038="            web => web);"
text039=" "
[COREGEN.VERILOG Component Instantiation.dpram_core]
type=template
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="dpram_core YourInstanceName ("
text007="    .addra(addra),"
text008="    .addrb(addrb),"
text009="    .clka(clka),"
text010="    .clkb(clkb),"
text011="    .dina(dina),"
text012="    .dinb(dinb),"
text013="    .douta(douta),"
text014="    .doutb(doutb),"
text015="    .wea(wea),"
text016="    .web(web));"
text017=""
text018=" "