?? dpram_core.xcp
字號:
# Xilinx CORE Generator 5.1i
SELECT Dual_Port_Block_Memory Virtex2P Xilinx,_Inc. 4.0
CSET primitive_selection = Optimize_For_Area
CSET port_a_active_clock_edge = Rising_Edge_Triggered
CSET port_a_additional_output_pipe_stages = 0
CSET port_b_active_clock_edge = Rising_Edge_Triggered
CSET port_a_enable_pin = false
CSET port_a_write_enable_polarity = Active_High
CSET port_a_initialization_pin_polarity = Active_High
CSET global_init_value = 0
CSET port_a_init_pin = false
CSET select_primitive = 16kx1
CSET port_b_enable_pin = false
CSET width_b = 16
CSET port_a_init_value = 0
CSET width_a = 16
CSET depth_b = 16
CSET port_a_register_inputs = false
CSET component_name = dpram_core
CSET depth_a = 16
CSET configuration_port_b = Read_And_Write
CSET configuration_port_a = Read_And_Write
CSET port_b_write_enable_polarity = Active_High
CSET port_b_init_value = 0
CSET port_b_handshaking_pins = false
CSET port_b_register_inputs = false
CSET port_b_initialization_pin_polarity = Active_High
CSET load_init_file = false
CSET port_a_handshaking_pins = false
CSET port_a_enable_pin_polarity = Active_High
CSET port_b_additional_output_pipe_stages = 0
CSET port_b_enable_pin_polarity = Active_High
CSET port_b_init_pin = false
CSET write_mode_port_b = Read_After_Write
CSET write_mode_port_a = Read_After_Write
GENERATE
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