vendor_name = ModelSim
source_file = 1, C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd
design_name = muxcntlr
instance = comp, ATA_SEL_aI, ATA_SEL, muxcntlr, 1
instance = comp, V33_ATA_DMARQ_aI, V33_ATA_DMARQ, muxcntlr, 1
instance = comp, UART_RXD1_DMARQ_a5_I, UART_RXD1_DMARQ~5, muxcntlr, 1
instance = comp, V33_CF_WAIT_BUSY_aI, V33_CF_WAIT_BUSY, muxcntlr, 1
instance = comp, NAND_BUSY_aI, NAND_BUSY, muxcntlr, 1
instance = comp, CFN_SEL_aI, CFN_SEL, muxcntlr, 1
instance = comp, V33_CF_PWR_ON_aI, V33_CF_PWR_ON, muxcntlr, 1
instance = comp, SelCF_a0_I, SelCF~0, muxcntlr, 1
instance = comp, V33_ATA_WAIT_BUSY_aI, V33_ATA_WAIT_BUSY, muxcntlr, 1
instance = comp, V33_SM_WAIT_BUSY_aI, V33_SM_WAIT_BUSY, muxcntlr, 1
instance = comp, V33_SM_CEZ_aI, V33_SM_CEZ, muxcntlr, 1
instance = comp, WAIT_BUSY_a39_I, WAIT_BUSY~39, muxcntlr, 1
instance = comp, WAIT_BUSY_a5_I, WAIT_BUSY~5, muxcntlr, 1
instance = comp, READ_OE_aI, READ_OE, muxcntlr, 1
instance = comp, ATA_DIR_aI, ATA_DIR, muxcntlr, 1
instance = comp, EM_CS2_aI, EM_CS2, muxcntlr, 1
instance = comp, EM_CS2_a14_I, EM_CS2~14, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_DIR_a68_I, V18_EM_DATA_BUF_DIR~68, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_DIR_a69_I, V18_EM_DATA_BUF_DIR~69, muxcntlr, 1
instance = comp, ATA_CS1_aI, ATA_CS1, muxcntlr, 1
instance = comp, ATA_CS0_aI, ATA_CS0, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_EN_a192_I, V18_EM_DATA_BUF_EN~192, muxcntlr, 1
instance = comp, UART_TXD1_DMACK_aI, UART_TXD1_DMACK, muxcntlr, 1
instance = comp, WRITE_WE_aI, WRITE_WE, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_EN_a191_I, V18_EM_DATA_BUF_EN~191, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_EN_a193_I, V18_EM_DATA_BUF_EN~193, muxcntlr, 1
instance = comp, V33_CF_INTRQ_EM_RNW_aI, V33_CF_INTRQ_EM_RNW, muxcntlr, 1
instance = comp, V33_ATA_INTRQ_EM_RNW_aI, V33_ATA_INTRQ_EM_RNW, muxcntlr, 1
instance = comp, INTRQ_EM_RNW_a2_I, INTRQ_EM_RNW~2, muxcntlr, 1
instance = comp, MSP430_INT_IN_aI, MSP430_INT_IN, muxcntlr, 1
instance = comp, V33_TIMER_IN_aI, V33_TIMER_IN, muxcntlr, 1
instance = comp, div8_a0_a_aI, div8[0], muxcntlr, 1
instance = comp, div8_a1_a_aI, div8[1], muxcntlr, 1
instance = comp, add_a38_I, add~38, muxcntlr, 1
instance = comp, div8_a2_a_aI, div8[2], muxcntlr, 1
instance = comp, ALE_EM_A1_aI, ALE_EM_A1, muxcntlr, 1
instance = comp, V33_SM_ALE_EM_A1_a10_I, V33_SM_ALE_EM_A1~10, muxcntlr, 1
instance = comp, CLE_EM_A2_aI, CLE_EM_A2, muxcntlr, 1
instance = comp, V33_SM_CLE_EM_A2_a10_I, V33_SM_CLE_EM_A2~10, muxcntlr, 1
instance = comp, V33_SM_WRITE_WE_a3_I, V33_SM_WRITE_WE~3, muxcntlr, 1
instance = comp, V33_SM_READ_OE_a4_I, V33_SM_READ_OE~4, muxcntlr, 1
instance = comp, V33_CF_WRITE_WE_a7_I, V33_CF_WRITE_WE~7, muxcntlr, 1
instance = comp, V33_CF_READ_OE_a7_I, V33_CF_READ_OE~7, muxcntlr, 1
instance = comp, V33_CF_ATA_CS0_a7_I, V33_CF_ATA_CS0~7, muxcntlr, 1
instance = comp, V33_CF_ATA_CS1_a7_I, V33_CF_ATA_CS1~7, muxcntlr, 1
instance = comp, ATA0_EM_BA0_aI, ATA0_EM_BA0, muxcntlr, 1
instance = comp, V33_CF_ATA0_EM_BA0_a12_I, V33_CF_ATA0_EM_BA0~12, muxcntlr, 1
instance = comp, ATA1_EM_BA1_aI, ATA1_EM_BA1, muxcntlr, 1
instance = comp, V33_CF_ATA1_EM_BA1_a12_I, V33_CF_ATA1_EM_BA1~12, muxcntlr, 1
instance = comp, ATA2_EM_A0_aI, ATA2_EM_A0, muxcntlr, 1
instance = comp, V33_CF_ATA2_EM_A0_a12_I, V33_CF_ATA2_EM_A0~12, muxcntlr, 1
instance = comp, V33_ATA_DA0_a10_I, V33_ATA_DA0~10, muxcntlr, 1
instance = comp, V33_ATA_DA1_a10_I, V33_ATA_DA1~10, muxcntlr, 1
instance = comp, V33_ATA_DA2_a10_I, V33_ATA_DA2~10, muxcntlr, 1
instance = comp, V33_ATA_DMACK_a3_I, V33_ATA_DMACK~3, muxcntlr, 1
instance = comp, V33_ATA_CS0_a3_I, V33_ATA_CS0~3, muxcntlr, 1
instance = comp, V33_ATA_CS1_a3_I, V33_ATA_CS1~3, muxcntlr, 1
instance = comp, V33_ATA_DIOR_a3_I, V33_ATA_DIOR~3, muxcntlr, 1
instance = comp, V33_ATA_DIOW_a3_I, V33_ATA_DIOW~3, muxcntlr, 1
instance = comp, V18_SYS_RESETZ_aI, V18_SYS_RESETZ, muxcntlr, 1
instance = comp, UART_RXD1_DMARQ_aI, UART_RXD1_DMARQ, muxcntlr, 1
instance = comp, WAIT_BUSY_aI, WAIT_BUSY, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_DIR_aI, V18_EM_DATA_BUF_DIR, muxcntlr, 1
instance = comp, V18_EM_DATA_BUF_EN_aI, V18_EM_DATA_BUF_EN, muxcntlr, 1
instance = comp, INTRQ_EM_RNW_aI, INTRQ_EM_RNW, muxcntlr, 1
instance = comp, MSP430_INT_OUT_aI, MSP430_INT_OUT, muxcntlr, 1
instance = comp, CPLD_TIMER_OUT_aI, CPLD_TIMER_OUT, muxcntlr, 1
instance = comp, V33_SM_ALE_EM_A1_aI, V33_SM_ALE_EM_A1, muxcntlr, 1
instance = comp, V33_SM_CLE_EM_A2_aI, V33_SM_CLE_EM_A2, muxcntlr, 1
instance = comp, V33_SM_WRITE_WE_aI, V33_SM_WRITE_WE, muxcntlr, 1
instance = comp, V33_SM_READ_OE_aI, V33_SM_READ_OE, muxcntlr, 1
instance = comp, V33_SM_SM_CEZ_aI, V33_SM_SM_CEZ, muxcntlr, 1
instance = comp, V33_CF_WRITE_WE_aI, V33_CF_WRITE_WE, muxcntlr, 1
instance = comp, V33_CF_READ_OE_aI, V33_CF_READ_OE, muxcntlr, 1
instance = comp, V33_CF_ATA_CS0_aI, V33_CF_ATA_CS0, muxcntlr, 1
instance = comp, V33_CF_ATA_CS1_aI, V33_CF_ATA_CS1, muxcntlr, 1
instance = comp, V33_CF_ATA0_EM_BA0_aI, V33_CF_ATA0_EM_BA0, muxcntlr, 1
instance = comp, V33_CF_ATA1_EM_BA1_aI, V33_CF_ATA1_EM_BA1, muxcntlr, 1
instance = comp, V33_CF_ATA2_EM_A0_aI, V33_CF_ATA2_EM_A0, muxcntlr, 1
instance = comp, V33_ATA_DA0_aI, V33_ATA_DA0, muxcntlr, 1
instance = comp, V33_ATA_DA1_aI, V33_ATA_DA1, muxcntlr, 1
instance = comp, V33_ATA_DA2_aI, V33_ATA_DA2, muxcntlr, 1
instance = comp, V33_ATA_DMACK_aI, V33_ATA_DMACK, muxcntlr, 1
instance = comp, V33_ATA_CS0_aI, V33_ATA_CS0, muxcntlr, 1
instance = comp, V33_ATA_CS1_aI, V33_ATA_CS1, muxcntlr, 1
instance = comp, V33_ATA_DIOR_aI, V33_ATA_DIOR, muxcntlr, 1
instance = comp, V33_ATA_DIOW_aI, V33_ATA_DIOW, muxcntlr, 1
instance = comp, V33_ATA_BUFF_DIR_aI, V33_ATA_BUFF_DIR, muxcntlr, 1
instance = comp, V33_ATA_BUFF_ENZ_aI, V33_ATA_BUFF_ENZ, muxcntlr, 1
instance = comp, V33_ATA_RESETn_aI, V33_ATA_RESETn, muxcntlr, 1
instance = comp, V33_SYS_RESETZ_aI, V33_SYS_RESETZ, muxcntlr, 1
instance = comp, V33_UART_RXD1_aI, V33_UART_RXD1, muxcntlr, 1
instance = comp, V33_UART_TXD1_aI, V33_UART_TXD1, muxcntlr, 1
instance = comp, SPAREIO1_aI, SPAREIO1, muxcntlr, 1
instance = comp, SPAREIO2_aI, SPAREIO2, muxcntlr, 1
instance = comp, SPAREIO3_aI, SPAREIO3, muxcntlr, 1