module module_b (CLK_TOP,TOP2B_IN,A2B_IN,A_AND_C_IN,
		MODB_DATA,MODB_CLK,MODB_OUT,
		B2TOP_OBUFT_T_OUT,B2C_OUT,B2A_OUT);


 
input CLK_TOP ; 
input A2B_IN ; 
input TOP2B_IN ; 
input A_AND_C_IN ; 
input MODB_DATA, MODB_CLK; 
output MODB_OUT; 
output B2A_OUT ; 
output B2TOP_OBUFT_T_OUT ; 
output B2C_OUT ; 
// add your declarations here 
reg Q0_OUT, Q1_OUT, Q2_OUT, Q3_OUT ; 
reg B2A_OUT, B2TOP_OBUFT_T_OUT, B2C_OUT ; 
reg MODB_OUT; 
wire AND4_OUT ; 
wire OR4_OUT ; 
// add your code here 
assign AND4_OUT = Q0_OUT && Q1_OUT && Q2_OUT && Q3_OUT ; 
assign OR4_OUT = !(Q0_OUT || Q1_OUT || Q2_OUT || Q3_OUT) ; //Do some change in debugging, then re-synthesis in incremental synthesis mode 
//assign OR4_OUT = Q0_OUT || Q1_OUT || Q2_OUT || Q3_OUT ;
always @ (posedge CLK_TOP) 
begin : TOP_CLK 
  Q0_OUT <= MODB_DATA ; 
  Q2_OUT <= TOP2B_IN ; 
  MODB_OUT <= OR4_OUT ; 
  B2A_OUT <= AND4_OUT ; 
end 
always @ (posedge MODB_CLK) 
begin : CLK_MODA 
  Q1_OUT <= A2B_IN ; 
  Q3_OUT <= A_AND_C_IN ; 
  B2TOP_OBUFT_T_OUT <= AND4_OUT ; 
  B2C_OUT <= OR4_OUT ; 
end 
endmodule