// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002


`timescale 1ns / 1ps

module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);

 input clk;
 input reset;
 input strstop;
output [6:0] onesout;
output [6:0] tensout;
output [9:0] tenthsout;

wire [3:0] Q;
wire XLXN_19;
wire XLXN_3;
wire XLXN_6;
wire XLXN_7;
wire clk_int;
wire clken_int;
wire [9:0] one_hot;
wire [3:0] ones;
wire q_thres;
wire rst_int;
wire [3:0] tens;

AND2 XLXI_15 (.I0(clken_int), .I1(q_thres), .O(XLXN_19));
cnt60 XLXI_12 (.clr(clk_int), .clk(rst_int), .ce(XLXN_19), .msbsec(ones[3:0]),
      .lsbsec(tens[3:0]));
dcm1 XLXI_16 (.CLKIN_IN(clk), .CLK0_OUT(clk_int));
decode XLXI_10 (.binary(Q[3:0]), .one_hot(one_hot[9:0]));
hex2led XLXI_13 (.HEX(ones[3:0]), .LED(onesout[6:0]));
hex2led XLXI_14 (.HEX(tens[3:0]), .LED(tensout[6:0]));
IBUF XLXI_2 (.I(reset), .O(XLXN_3));
   // synthesis attribute IOSTANDARD of XLXI_2 is "LVTTL"
IBUF XLXI_6 (.I(strstop), .O(XLXN_6));
   // synthesis attribute IOSTANDARD of XLXI_6 is "LVTTL"
INV XLXI_7 (.I(XLXN_6), .O(XLXN_7));
outs3 XLXI_11 (.inputs(one_hot[9:0]), .outs(tenthsout[9:0]));
stmach_v XLXI_5 (.CLK(clk_int), .reset(XLXN_3), .strstop(XLXN_7),
      .clkout(clken_int), .rst(rst_int));
tenths XLXI_9 (.CE(clken_int), .CLK(clk_int), .Q_THRESH0(q_thres), .Q(Q[3:0]),
      .AINIT(rst_int));
endmodule