# Xilinx CORE Generator 5.1i
# Username = wcheng
# COREGenPath = J:\eda\Xilinx\coregen
# ProjectPath = J:\projects\ISE\ISEexamples\wtut_sc
# ExpandedProjectPath = J:\projects\ISE\ISEexamples\wtut_sc
# OverwriteFiles = Default
# Core name: tenths
# Number of Primitives in design: 25
# Number of CLBs used in design: 3
# Number of Slices used in design: 8
# Number of LUT sites used in design: 12
# Number of LUTs used in design: 12
# Number of REG used in design: 6
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "default" = (0, 0) to (1, 3) in CLBs
# 
SET BusFormat = BusFormatAngleBracket
SET SimulationOutputProducts = Verilog VHDL
SET XilinxFamily = Virtex2
SET OutputOption = DesignFlow
SET DesignFlow = Vhdl
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SELECT Binary_Counter Virtex2 Xilinx,_Inc. 5.0
CSET ce_override_for_load = false
CSET async_init_value = 1
CSET create_rpm = true
CSET clock_enable = true
CSET load = false
CSET ce_overrides = sync_controls_override_ce
CSET load_sense = active_high
CSET sync_init_value = 0
CSET operation = up
CSET threshold_1 = false
CSET threshold_0 = true
CSET count_style = count_by_constant
CSET restrict_count = true
CSET count_by_value = 1
CSET component_name = tenths
CSET threshold_early = true
CSET asynchronous_settings = init
CSET threshold_1_value = MAX
CSET count_to_value = A
CSET threshold_0_value = A
CSET threshold_options = registered
CSET set_clear_priority = clear_overrides_set
CSET output_width = 4
CSET synchronous_settings = none
GENERATE