?? uc_interface.srr
字號(hào):
$ Start of Compile
#Mon Jul 19 18:36:03 2004
Synplicity VHDL Compiler, version 7.1, Build 158R, built Apr 18 2002
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
VHDL syntax check successful!
Synthesizing work.uc_interface.behaviour
@N:"D:\My_Design\I2C\source\uc_interface.vhd":111:16:111:17|Using sequential encoding for type state_type
@W:"D:\My_Design\I2C\source\uc_interface.vhd":267:35:267:43|Signal prs_state in the sensitivity list is not used in the process
Post processing for work.uc_interface.behaviour
@W:"D:\My_Design\I2C\source\uc_interface.vhd":331:2:331:3|Optimizing register bit madr(0) to a constant 0
@N:"D:\My_Design\I2C\source\uc_interface.vhd":183:2:183:3|Trying to extract state machine for register prs_state
Extracted state machine for register prs_state
State machine has 4 reachable states with original encodings of:
00
01
10
11
@END
Process took 0.266 seconds realtime, 0.265 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.1, Build 152R, built Apr 9 2002
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
Encoding state machine work.uC_interface(behaviour)-prs_state_h.prs_state[0:3]
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Net buffering Report for view:work.uC_interface(behaviour):
No nets needed buffering.
@N|The option to pack flops in the IOB has not been specified
Writing Analyst data base D:\My_Design\I2C\synplify\rev_1\uc_interface.srm
Writing EDIF Netlist and constraint files
Found clock clk with period 1000.00ns
##### START TIMING REPORT #####
# Timing Report written on Mon Jul 19 18:36:04 2004
#
Top view: uC_interface
Slew propagation mode: worst
Paths requested: 5
Constraint File(s):
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.
Performance Summary
*******************
Worst slack in design: 989.769
Requested Estimated Requested Estimated Clock
Starting Clock Frequency Frequency Period Period Slack Type
-----------------------------------------------------------------------------------------------
clk 1.0 MHz 97.7 MHz 1000.000 10.231 989.769 inferred
System 1.0 MHz 108.2 MHz 1000.000 9.238 990.762 system
===============================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
clk clk | 1000.000 989.769 | No paths - | No paths - | No paths -
==========================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-------------------------------------------------------------------------------------
addr_bus[0] clk (rising) NA 0.000 993.655 993.655
addr_bus[1] clk (rising) NA 0.000 995.270 995.270
addr_bus[2] clk (rising) NA 0.000 995.270 995.270
addr_bus[3] clk (rising) NA 0.000 995.047 995.047
addr_bus[4] clk (rising) NA 0.000 995.047 995.047
addr_bus[5] clk (rising) NA 0.000 993.655 993.655
addr_bus[6] clk (rising) NA 0.000 993.655 993.655
addr_bus[7] clk (rising) NA 0.000 993.655 993.655
addr_bus[8] clk (rising) NA 0.000 995.624 995.624
addr_bus[9] clk (rising) NA 0.000 995.624 995.624
addr_bus[10] clk (rising) NA 0.000 995.624 995.624
addr_bus[11] clk (rising) NA 0.000 995.624 995.624
addr_bus[12] clk (rising) NA 0.000 995.624 995.624
addr_bus[13] clk (rising) NA 0.000 995.624 995.624
addr_bus[14] clk (rising) NA 0.000 995.624 995.624
addr_bus[15] clk (rising) NA 0.000 994.232 994.232
addr_bus[16] clk (rising) NA 0.000 994.232 994.232
addr_bus[17] clk (rising) NA 0.000 995.624 995.624
addr_bus[18] clk (rising) NA 0.000 995.624 995.624
addr_bus[19] clk (rising) NA 0.000 994.232 994.232
addr_bus[20] clk (rising) NA 0.000 994.232 994.232
addr_bus[21] clk (rising) NA 0.000 994.232 994.232
addr_bus[22] clk (rising) NA 0.000 994.232 994.232
addr_bus[23] clk (rising) NA 0.000 995.624 995.624
as clk (rising) NA 0.000 997.285 997.285
clk NA NA NA NA NA
data_bus[0] clk (rising) NA 0.000 997.861 997.861
data_bus[1] clk (rising) NA 0.000 997.443 997.443
data_bus[2] clk (rising) NA 0.000 996.662 996.662
data_bus[3] clk (rising) NA 0.000 997.312 997.312
data_bus[4] clk (rising) NA 0.000 996.662 996.662
data_bus[5] clk (rising) NA 0.000 996.662 996.662
data_bus[6] clk (rising) NA 0.000 997.312 997.312
data_bus[7] clk (rising) NA 0.000 997.312 997.312
ds clk (rising) NA 0.000 1000.000 1000.000
maas clk (rising) NA 0.000 995.077 995.077
mal clk (rising) NA 0.000 995.077 995.077
mbb clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[0] clk (rising) NA 0.000 996.469 996.469
mbdr_i2c[1] clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[2] clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[3] clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[4] clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[5] clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[6] clk (rising) NA 0.000 995.077 995.077
mbdr_i2c[7] clk (rising) NA 0.000 995.077 995.077
mcf clk (rising) NA 0.000 995.077 995.077
mif System (rising) NA 0.000 990.762 990.762
msta_rst clk (rising) NA 0.000 995.601 995.601
r_w clk (rising) NA 0.000 989.769 989.769
reset NA NA NA NA NA
rsta_rst clk (rising) NA 0.000 995.601 995.601
rxak clk (rising) NA 0.000 996.469 996.469
srw clk (rising) NA 0.000 995.077 995.077
=====================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-----------------------------------------------------------------------------------
data_bus[0] clk (rising) NA 10.231 1000.000 989.769
data_bus[1] clk (rising) NA 10.231 1000.000 989.769
data_bus[2] clk (rising) NA 10.231 1000.000 989.769
data_bus[3] clk (rising) NA 10.231 1000.000 989.769
data_bus[4] clk (rising) NA 10.231 1000.000 989.769
data_bus[5] clk (rising) NA 10.231 1000.000 989.769
data_bus[6] clk (rising) NA 10.231 1000.000 989.769
data_bus[7] clk (rising) NA 10.231 1000.000 989.769
dtack clk (rising) NA 0.000 1000.000 1000.000
irq clk (rising) NA 9.453 1000.000 990.547
madr[0] NA NA NA NA NA
madr[1] clk (rising) NA 7.271 1000.000 992.729
madr[2] clk (rising) NA 7.271 1000.000 992.729
madr[3] clk (rising) NA 7.271 1000.000 992.729
madr[4] clk (rising) NA 7.271 1000.000 992.729
madr[5] clk (rising) NA 7.271 1000.000 992.729
madr[6] clk (rising) NA 7.271 1000.000 992.729
madr[7] clk (rising) NA 7.271 1000.000 992.729
mal_bit_reset clk (rising) NA 7.271 1000.000 992.729
mbcr_wr clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[0] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[1] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[2] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[3] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[4] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[5] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[6] clk (rising) NA 0.000 1000.000 1000.000
mbdr_micro[7] clk (rising) NA 0.000 1000.000 1000.000
mbdr_read clk (rising) NA 0.000 1000.000 1000.000
men clk (rising) NA 7.271 1000.000 992.729
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