/*
*Author hejun
*Date   2006_7_12 
*/

/*SystemClock=180MHz*/
//F_out=10MHz 	FrqDWord=238609294;	W1=0x0e; W2=0x38; W3=0xe3; W4=0x83;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=5MHz 	FrqDWord=119304647;	W1=0x07; W2=0x1c; W3=0x71; W4=0xc7;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=1MHz 	FrqDWord=23860929;	W1=0x01; W2=0x6c; W3=0x16; W4=0xc1;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=100kHz 	FrqDWord=2386093;	W1=0x00; W2=0x24; W3=0x68; W4=0xad;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=50kHz 	FrqDWord=1193046;	W1=0x00; W2=0x12; W3=0x34; W4=0x56;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=10kHz 	FrqDWord=238609;	W1=0x00; W2=0x03; W3=0xa4; W4=0x11;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=5kHz 	FrqDWord=119305;	W1=0x00; W2=0x01; W3=0xd2; W4=0x09;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=1kHz 	FrqDWord=23861; 	W1=0x00; W2=0x00; W3=0x5d; W4=0x35;//(W1=Freq–b31__Freq–b3Freq–b24)
//F_out=100Hz 	FrqDWord=2386; 		W1=0x00; W2=0x00; W3=0x09; W4=0x52;//(W1=Freq–b31__Freq–b3Freq–b24)
#include <at89X52.h>
#define RESET  P1_0
#define W_CLK  P1_1
#define FQ_UD  P1_2
#define DDSData		P2 
#define CLR_WCLK()   W_CLK = 0
#define CLR_FQUD()   FQ_UD = 0
#define CLR_RESET()  RESET = 0
#define SET_WCLK()   W_CLK = 1
#define SET_FQUD()   FQ_UD = 1
#define SET_RESET()  RESET = 1
unsigned char W0,W1,W2,W3,W4;   

void debug()
{
	unsigned int j;
 	unsigned int i;
	
	for(j=100;j>0;j--)
	for(i=250;i>0;i--);
	
	P0_0= 0;
	P0_1= 1;

	P1_4=1;
	while(P1_4);
	
	P0_0= 1;
	P0_1= 0;
}
void delay()
{
	unsigned char i;
	for (i=1;i<255;i++);
	//for (i=1;i<=0xff;i++);
}

void init()
{ 
    CLR_RESET();
    delay();
    SET_RESET();
    delay();
    delay();
    delay();
    delay();
    delay();
    CLR_RESET();   //AD9851復位   
}

void load_40bit_data()
{
    
    CLR_WCLK(); 
    CLR_FQUD();
    
    CLR_WCLK();           //Load W1 to shifting register
    DDSData= W0;
    delay();
    SET_WCLK();
    delay();
    	debug();          //debug 1   	P2=00000001  P1_1=1  P1_2=0
    
    CLR_WCLK();          //Load W1 to shifting register
    DDSData= W1;
    delay();	
    SET_WCLK();
    delay();
        debug();	//debug 2	P2=00000001   P1_1=1  P1_2=0
    
    CLR_WCLK();  	 //Load W2 to shifting register
    DDSData= W2;
    delay();
    SET_WCLK();
    delay();
        debug();	//debug 3         P2=01101100  P1_1=1  P1_2=0
    
    CLR_WCLK();		 //Load W3 to shifting register
    DDSData= W3;
    delay();
    SET_WCLK();
    delay();
        debug();	//debug 4         P2=00010110   P1_1=1  P1_2=0
    
    CLR_WCLK();		 //Load W4 to shifting register
    DDSData= W4;
    delay();
    SET_WCLK();
    delay();
        debug();	//debug 5       P2=11000001     P1_1=1  P1_2=0
    
    CLR_WCLK();
    delay();
    delay();
    delay();
    SET_FQUD();
        debug();	//debug 6	P2=11000001   P1_1=0 P1_2=1
    delay();
    delay();
    delay();
    delay();
    delay();
    delay();
    CLR_FQUD();       //Load 40_bit data to the dds core register
}


void main()
{
	
	W0 = 0x01;				//Enable 6′ REFCLK Multiplier 
	W1=0x01; W2=0x6c; W3=0x16; W4=0xc1;     //f_out=1MHz
	init();

	delay();
	delay();

	load_40bit_data();
	while(1)P0=0;
}