?? sine_32.rpt
字號:
| | | | | | | +----------------- LC20 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
| | | | | | | | +--------------- LC17 q_3
| | | | | | | | | +------------- LC18 cnt4
| | | | | | | | | | +----------- LC32 ~3988~1
| | | | | | | | | | | +--------- LC31 ~4000~1
| | | | | | | | | | | | +------- LC25 ~4006~1
| | | | | | | | | | | | | +----- LC26 ~4012~1
| | | | | | | | | | | | | | +--- LC27 ~4012~2
| | | | | | | | | | | | | | | +- LC28 ~4018~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> - - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
LC20 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
LC17 -> * * * * * * * * * * * * * * * - | * * | <-- q_3
LC18 -> - * * * * * - * * * * * * * * * | * * | <-- cnt4
LC32 -> - - - - * - - - - - - - - - - - | - * | <-- ~3988~1
LC26 -> - - * - - - - - - - - - - - - - | - * | <-- ~4012~1
LC27 -> - - * - - - - - - - - - - - - - | - * | <-- ~4012~2
LC28 -> - * - - - - - - - - - - - - - - | - * | <-- ~4018~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
5 -> - - - - - - - - * * - - - - - - | * * | <-- rst
4 -> - * * * * * - - - - * * * * * * | * * | <-- sel
LC3 -> * - * * * * * * * * * * * * * * | * * | <-- cnt2
LC1 -> * * * * * * * * * * * * * * * * | * * | <-- cnt1
LC2 -> * * * * * * * * * * * * * * * * | * * | <-- cnt0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\sine_32.rpt
sine_32
** EQUATIONS **
clk : INPUT;
rst : INPUT;
sel : INPUT;
-- Node name is ':17' = 'cnt0'
-- Equation name is 'cnt0', location is LC002, type is buried.
cnt0 = TFFE( VCC, GLOBAL( clk), !rst, VCC, VCC);
-- Node name is ':16' = 'cnt1'
-- Equation name is 'cnt1', location is LC001, type is buried.
cnt1 = TFFE( cnt0, GLOBAL( clk), !rst, VCC, VCC);
-- Node name is ':15' = 'cnt2'
-- Equation name is 'cnt2', location is LC003, type is buried.
cnt2 = TFFE( _EQ001, GLOBAL( clk), !rst, VCC, VCC);
_EQ001 = cnt0 & cnt1;
-- Node name is ':13' = 'cnt4'
-- Equation name is 'cnt4', location is LC018, type is buried.
cnt4 = DFFE( _EQ002 $ _LC020, GLOBAL( clk), !rst, VCC, VCC);
_EQ002 = cnt0 & cnt1 & cnt2 & cnt4 & _LC020 & q_3;
-- Node name is 'data_out0'
-- Equation name is 'data_out0', location is LC030, type is output.
data_out0 = LCELL( _EQ003 $ !cnt1);
_EQ003 = !cnt0 & !cnt1 & !cnt2 & q_3
# cnt0 & !cnt2;
-- Node name is 'data_out1'
-- Equation name is 'data_out1', location is LC029, type is output.
data_out1 = LCELL( _EQ004 $ !_LC028);
_EQ004 = !cnt0 & !cnt1 & cnt4 & !_LC028 & q_3 & !sel
# !cnt0 & !cnt1 & !cnt4 & !_LC028 & q_3 & sel
# cnt0 & cnt4 & !_LC028 & sel
# cnt1 & cnt4 & !_LC028 & sel;
-- Node name is 'data_out2'
-- Equation name is 'data_out2', location is LC023, type is output.
data_out2 = LCELL( _EQ005 $ !cnt4);
_EQ005 = !_LC026 & !_LC027 & _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!cnt0 & !cnt2 & !cnt4 & !q_3 & sel);
_X002 = EXP(!cnt0 & cnt1 & !cnt2 & cnt4 & !q_3 & sel);
_X003 = EXP(!cnt0 & !cnt1 & !cnt2 & !cnt4 & !q_3);
_X004 = EXP( cnt0 & cnt1 & !q_3 & !sel);
-- Node name is 'data_out3'
-- Equation name is 'data_out3', location is LC006, type is output.
data_out3 = LCELL( _EQ006 $ !cnt4);
_EQ006 = !_LC025 & _X003 & _X005 & _X006 & _X007 & _X008 & _X009;
_X003 = EXP(!cnt0 & !cnt1 & !cnt2 & !cnt4 & !q_3);
_X005 = EXP( cnt0 & cnt2 & !q_3 & !sel);
_X006 = EXP( cnt0 & !cnt1 & !cnt2 & cnt4 & !sel);
_X007 = EXP(!cnt1 & !cnt2 & !cnt4 & !sel);
_X008 = EXP(!cnt0 & !cnt1 & !cnt4 & !sel);
_X009 = EXP(!cnt0 & cnt1 & sel);
-- Node name is 'data_out4'
-- Equation name is 'data_out4', location is LC005, type is output.
data_out4 = LCELL( _EQ007 $ !cnt4);
_EQ007 = !_LC031 & _X003 & _X006 & _X007 & _X010 & _X011;
_X003 = EXP(!cnt0 & !cnt1 & !cnt2 & !cnt4 & !q_3);
_X006 = EXP( cnt0 & !cnt1 & !cnt2 & cnt4 & !sel);
_X007 = EXP(!cnt1 & !cnt2 & !cnt4 & !sel);
_X010 = EXP( cnt1 & cnt2 & !sel);
_X011 = EXP(!cnt0 & !cnt4 & !sel);
-- Node name is 'data_out5'
-- Equation name is 'data_out5', location is LC019, type is output.
data_out5 = LCELL( _EQ008 $ !cnt4);
_EQ008 = _X003 & _X005 & _X012 & _X013 & _X014 & _X015 & _X016;
_X003 = EXP(!cnt0 & !cnt1 & !cnt2 & !cnt4 & !q_3);
_X005 = EXP( cnt0 & cnt2 & !q_3 & !sel);
_X012 = EXP(!cnt2 & q_3 & !sel);
_X013 = EXP( cnt0 & cnt2 & q_3 & sel);
_X014 = EXP( cnt0 & !cnt2 & !q_3 & sel);
_X015 = EXP(!cnt0 & !cnt1 & cnt2 & sel);
_X016 = EXP(!cnt0 & cnt1 & !sel);
-- Node name is 'data_out6'
-- Equation name is 'data_out6', location is LC024, type is output.
data_out6 = LCELL( _EQ009 $ !cnt4);
_EQ009 = !_LC032 & _X001 & _X002 & _X003 & _X004 & _X012;
_X001 = EXP(!cnt0 & !cnt2 & !cnt4 & !q_3 & sel);
_X002 = EXP(!cnt0 & cnt1 & !cnt2 & cnt4 & !q_3 & sel);
_X003 = EXP(!cnt0 & !cnt1 & !cnt2 & !cnt4 & !q_3);
_X004 = EXP( cnt0 & cnt1 & !q_3 & !sel);
_X012 = EXP(!cnt2 & q_3 & !sel);
-- Node name is 'data_out7'
-- Equation name is 'data_out7', location is LC021, type is output.
data_out7 = LCELL( _EQ010 $ VCC);
_EQ010 = !cnt0 & !cnt1 & !cnt2 & !q_3
# cnt4 & !sel
# !cnt4 & sel;
-- Node name is 'q_3' = 'cnt3'
-- Equation name is 'q_3', location is LC017, type is output.
q_3 = DFFE( _EQ011 $ _LC022, GLOBAL( clk), !rst, VCC, VCC);
_EQ011 = cnt0 & cnt1 & cnt2 & cnt4 & _LC022 & q_3;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( q_3 $ _EQ012);
_EQ012 = cnt0 & cnt1 & cnt2;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( cnt4 $ _EQ013);
_EQ013 = cnt0 & cnt1 & cnt2 & q_3;
-- Node name is '~3988~1'
-- Equation name is '~3988~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ014 $ GND);
_EQ014 = cnt0 & !cnt1 & !cnt2 & cnt4 & !q_3 & sel
# !cnt1 & !cnt2 & !cnt4 & !q_3 & sel
# cnt1 & cnt2 & q_3 & sel
# !cnt1 & cnt2 & !sel
# cnt2 & !q_3 & !sel;
-- Node name is '~4000~1'
-- Equation name is '~4000~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ015 $ GND);
_EQ015 = !cnt1 & !cnt2 & cnt4 & q_3 & !sel
# cnt0 & !cnt1 & cnt2 & sel
# cnt0 & cnt1 & !cnt2 & sel
# !cnt0 & cnt1 & cnt4 & !sel
# !cnt0 & cnt2 & cnt4 & !sel;
-- Node name is '~4006~1'
-- Equation name is '~4006~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ016 $ GND);
_EQ016 = cnt0 & !cnt1 & cnt2 & q_3 & sel
# !cnt0 & !cnt1 & cnt2 & cnt4 & !sel
# !cnt0 & !cnt1 & cnt4 & q_3 & !sel
# cnt0 & cnt1 & q_3 & !sel
# cnt1 & !cnt2 & !q_3 & sel;
-- Node name is '~4012~1'
-- Equation name is '~4012~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ017 $ GND);
_EQ017 = cnt1 & cnt2 & cnt4 & q_3 & sel
# !cnt0 & cnt2 & !cnt4 & q_3 & sel
# cnt0 & !cnt1 & cnt4 & !q_3 & sel
# !cnt0 & !cnt1 & cnt2 & cnt4 & sel
# cnt0 & cnt1 & q_3 & sel;
-- Node name is '~4012~2'
-- Equation name is '~4012~2', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ018 $ GND);
_EQ018 = cnt0 & !cnt1 & q_3 & !sel
# cnt1 & cnt2 & !q_3 & !sel
# !cnt1 & !cnt4 & !q_3 & sel
# !cnt0 & !cnt2 & q_3 & !sel;
-- Node name is '~4018~1'
-- Equation name is '~4018~1', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ019 $ GND);
_EQ019 = cnt0 & cnt1 & !cnt2
# cnt0 & !cnt4 & !sel
# cnt1 & !cnt4 & !sel
# !cnt1 & cnt2;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X003 occurs in LABs A, B
-- _X005 occurs in LABs A, B
Project Information d:\laserinterface\cpld\sine_32.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,456K
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