-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ066);
  _EQ066 =  _LC8_B16 & !q427 &  q428
         # !_LC4_B9 &  _LC8_B16 &  q428
         #  _LC4_B9 &  _LC8_B16 &  q427 & !q428;

-- Node name is ':458' 
-- Equation name is '_LC5_B9', type is buried 
_LC5_B9  = LCELL( _EQ067);
  _EQ067 = !_LC4_B9 &  _LC8_B16 &  q427
         #  _LC4_B9 &  _LC8_B16 & !q427;

-- Node name is ':467' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = LCELL( _EQ068);
  _EQ068 =  _LC8_B16 & !q425 &  q426
         # !_LC4_B12 &  _LC8_B16 &  q426
         #  _LC4_B12 &  _LC8_B16 &  q425 & !q426;

-- Node name is ':476' 
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ069);
  _EQ069 = !_LC4_B12 &  _LC8_B16 &  q425
         #  _LC4_B12 &  _LC8_B16 & !q425;

-- Node name is ':485' 
-- Equation name is '_LC2_B12', type is buried 
_LC2_B12 = LCELL( _EQ070);
  _EQ070 =  _LC8_B16 & !q423 &  q424
         # !_LC5_B12 &  _LC8_B16 &  q424
         #  _LC5_B12 &  _LC8_B16 &  q423 & !q424;

-- Node name is ':494' 
-- Equation name is '_LC7_B12', type is buried 
_LC7_B12 = LCELL( _EQ071);
  _EQ071 = !_LC5_B12 &  _LC8_B16 &  q423
         #  _LC5_B12 &  _LC8_B16 & !q423;

-- Node name is ':503' 
-- Equation name is '_LC6_B1', type is buried 
_LC6_B1  = LCELL( _EQ072);
  _EQ072 =  _LC8_B16 & !q421 &  q422
         # !_LC5_B23 &  _LC8_B16 &  q422
         #  _LC5_B23 &  _LC8_B16 &  q421 & !q422;

-- Node name is ':512' 
-- Equation name is '_LC6_B12', type is buried 
_LC6_B12 = LCELL( _EQ073);
  _EQ073 = !_LC5_B23 &  _LC8_B16 &  q421
         #  _LC5_B23 &  _LC8_B16 & !q421;

-- Node name is ':521' 
-- Equation name is '_LC3_B23', type is buried 
_LC3_B23 = LCELL( _EQ074);
  _EQ074 =  _LC8_B16 & !q419 &  q420
         # !_LC4_B22 &  _LC8_B16 &  q420
         #  _LC4_B22 &  _LC8_B16 &  q419 & !q420;

-- Node name is ':530' 
-- Equation name is '_LC6_B23', type is buried 
_LC6_B23 = LCELL( _EQ075);
  _EQ075 = !_LC4_B22 &  _LC8_B16 &  q419
         #  _LC4_B22 &  _LC8_B16 & !q419;

-- Node name is ':539' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = LCELL( _EQ076);
  _EQ076 = !_LC3_B22 &  _LC8_B16 &  q418
         #  _LC3_B22 &  _LC8_B16 & !q418;

-- Node name is ':548' 
-- Equation name is '_LC1_B22', type is buried 
_LC1_B22 = LCELL( _EQ077);
  _EQ077 =  _LC8_B16 & !q416 &  q417
         #  _LC8_B16 & !_LC8_B21 &  q417
         #  _LC8_B16 &  _LC8_B21 &  q416 & !q417;

-- Node name is ':557' 
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = LCELL( _EQ078);
  _EQ078 =  _LC8_B16 & !_LC8_B21 &  q416
         #  _LC8_B16 &  _LC8_B21 & !q416;

-- Node name is ':566' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = LCELL( _EQ079);
  _EQ079 =  _LC8_B16 & !q414 &  q415
         # !_LC7_B21 &  _LC8_B16 &  q415
         #  _LC7_B21 &  _LC8_B16 &  q414 & !q415;

-- Node name is ':575' 
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = LCELL( _EQ080);
  _EQ080 =  _LC8_B16 & !q413 &  q414
         # !_LC2_B17 &  _LC8_B16 &  q414
         #  _LC2_B17 &  _LC8_B16 &  q413 & !q414;

-- Node name is ':584' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ081);
  _EQ081 = !_LC2_B17 &  _LC8_B16 &  q413
         #  _LC2_B17 &  _LC8_B16 & !q413;

-- Node name is ':593' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = LCELL( _EQ082);
  _EQ082 =  _LC8_B16 & !q411 &  q412
         # !_LC6_B17 &  _LC8_B16 &  q412
         #  _LC6_B17 &  _LC8_B16 &  q411 & !q412;

-- Node name is ':602' 
-- Equation name is '_LC5_B17', type is buried 
_LC5_B17 = LCELL( _EQ083);
  _EQ083 =  _LC8_B16 & !q410 &  q411
         # !_LC1_B20 &  _LC8_B16 &  q411
         #  _LC1_B20 &  _LC8_B16 &  q410 & !q411;

-- Node name is ':611' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = LCELL( _EQ084);
  _EQ084 = !_LC1_B20 &  _LC8_B16 &  q410
         #  _LC1_B20 &  _LC8_B16 & !q410;

-- Node name is ':620' 
-- Equation name is '_LC7_B20', type is buried 
_LC7_B20 = LCELL( _EQ085);
  _EQ085 =  _LC8_B16 & !q48 &  q49
         # !_LC4_B20 &  _LC8_B16 &  q49
         #  _LC4_B20 &  _LC8_B16 &  q48 & !q49;

-- Node name is ':629' 
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = LCELL( _EQ086);
  _EQ086 =  en & !_LC1_B13 & !_LC4_B20 &  q48
         #  en & !_LC1_B13 &  _LC4_B20 & !q48;

-- Node name is ':638' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = LCELL( _EQ087);
  _EQ087 = !_LC8_B14 &  _LC8_B16 &  q47
         #  _LC8_B14 &  _LC8_B16 & !q47;

-- Node name is ':647' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ088);
  _EQ088 =  _LC8_B16 & !q45 &  q46
         # !_LC4_B14 &  _LC8_B16 &  q46
         #  _LC4_B14 &  _LC8_B16 &  q45 & !q46;

-- Node name is ':656' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = LCELL( _EQ089);
  _EQ089 =  _LC8_B16 & !q44 &  q45
         #  _LC8_B16 & !_LC8_B18 &  q45
         #  _LC8_B16 &  _LC8_B18 &  q44 & !q45;

-- Node name is ':665' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ090);
  _EQ090 =  _LC8_B16 & !_LC8_B18 &  q44
         #  _LC8_B16 &  _LC8_B18 & !q44;

-- Node name is ':674' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ091);
  _EQ091 =  _LC8_B16 & !q42 &  q43
         # !_LC5_B18 &  _LC8_B16 &  q43
         #  _LC5_B18 &  _LC8_B16 &  q42 & !q43;

-- Node name is '~683~1' 
-- Equation name is '~683~1', location is LC8_B16, type is buried.
-- synthesized logic cell 
_LC8_B16 = LCELL( _EQ092);
  _EQ092 =  en & !_LC1_B13;

-- Node name is ':683' 
-- Equation name is '_LC3_B18', type is buried 
_LC3_B18 = LCELL( _EQ093);
  _EQ093 =  _LC8_B16 & !q41 &  q42
         #  _LC8_B16 & !q40 &  q42
         #  _LC8_B16 &  q40 &  q41 & !q42;

-- Node name is ':692' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ094);
  _EQ094 =  en & !_LC1_B13 & !q40 &  q41
         #  en & !_LC1_B13 &  q40 & !q41;



Project Information                               f:\study\vhdl\clock\cnt4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,587K