!_LC2_C18 = _LC2_C18~NOT;
_LC2_C18~NOT = LCELL( _EQ100);
  _EQ100 = !_LC4_C18 & !secl23
         #  _LC5_B14 & !secl23
         # !_LC4_C18 & !_LC5_B14;

-- Node name is ':962' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ101);
  _EQ101 =  _LC7_B14 &  min102
         #  _LC2_B14 &  min2;

-- Node name is ':965' 
-- Equation name is '_LC6_C19', type is buried 
_LC6_C19 = LCELL( _EQ102);
  _EQ102 =  _LC3_B14 & !q62 &  sec102
         #  _LC5_C19 &  q62
         # !_LC3_B14 &  _LC5_C19;

-- Node name is ':968' 
-- Equation name is '_LC7_C19', type is buried 
_LC7_C19 = LCELL( _EQ103);
  _EQ103 = !_LC1_B14 &  _LC6_C19
         #  _LC1_B14 &  sec2;

-- Node name is ':971' 
-- Equation name is '_LC8_C19', type is buried 
_LC8_C19 = LCELL( _EQ104);
  _EQ104 =  _LC7_C19 & !_LC8_B14
         #  _LC8_B14 &  secl12;

-- Node name is ':974' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ105);
  _EQ105 = !_LC5_B14 &  _LC8_C19
         #  _LC5_B14 &  secl22;

-- Node name is ':983' 
-- Equation name is '_LC5_C18', type is buried 
!_LC5_C18 = _LC5_C18~NOT;
_LC5_C18~NOT = LCELL( _EQ106);
  _EQ106 = !min1 & !min101
         # !_LC7_B14 & !min1
         # !_LC2_B14 & !min101
         # !_LC2_B14 & !_LC7_B14;

-- Node name is ':986' 
-- Equation name is '_LC6_C18', type is buried 
!_LC6_C18 = _LC6_C18~NOT;
_LC6_C18~NOT = LCELL( _EQ107);
  _EQ107 =  _LC3_B14 & !q62 & !sec101
         # !_LC5_C18 &  q62
         # !_LC3_B14 & !_LC5_C18
         # !_LC5_C18 & !sec101;

-- Node name is ':989' 
-- Equation name is '_LC7_C18', type is buried 
!_LC7_C18 = _LC7_C18~NOT;
_LC7_C18~NOT = LCELL( _EQ108);
  _EQ108 = !_LC6_C18 & !sec1
         #  _LC1_B14 & !sec1
         # !_LC1_B14 & !_LC6_C18;

-- Node name is ':992' 
-- Equation name is '_LC8_C18', type is buried 
!_LC8_C18 = _LC8_C18~NOT;
_LC8_C18~NOT = LCELL( _EQ109);
  _EQ109 = !_LC7_C18 & !secl11
         #  _LC8_B14 & !secl11
         # !_LC7_C18 & !_LC8_B14;

-- Node name is ':995' 
-- Equation name is '_LC1_C18', type is buried 
!_LC1_C18 = _LC1_C18~NOT;
_LC1_C18~NOT = LCELL( _EQ110);
  _EQ110 = !_LC8_C18 & !secl21
         #  _LC5_B14 & !secl21
         # !_LC5_B14 & !_LC8_C18;

-- Node name is ':1004' 
-- Equation name is '_LC3_C19', type is buried 
_LC3_C19 = LCELL( _EQ111);
  _EQ111 =  _LC7_B14 &  min100
         #  _LC2_B14 &  min0;

-- Node name is ':1007' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = LCELL( _EQ112);
  _EQ112 =  _LC3_B14 & !q62 &  sec100
         #  _LC3_C19 &  q62
         # !_LC3_B14 &  _LC3_C19;

-- Node name is ':1010' 
-- Equation name is '_LC1_C19', type is buried 
_LC1_C19 = LCELL( _EQ113);
  _EQ113 = !_LC1_B14 &  _LC4_C19
         #  _LC1_B14 &  sec0;

-- Node name is ':1013' 
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ114);
  _EQ114 =  _LC1_C19 & !_LC8_B14
         #  _LC8_B14 &  secl10;

-- Node name is ':1016' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = LCELL( _EQ115);
  _EQ115 =  _LC2_C13 & !_LC5_B14
         #  _LC5_B14 &  secl20;

-- Node name is '~1281~1' 
-- Equation name is '~1281~1', location is LC7_C15, type is buried.
-- synthesized logic cell 
_LC7_C15 = LCELL( _EQ116);
  _EQ116 =  _LC1_C18 & !_LC2_C18 & !_LC2_C19
         # !_LC1_C13 & !_LC1_C18 & !_LC2_C18 &  _LC2_C19;

-- Node name is ':1290' 
-- Equation name is '_LC6_C15', type is buried 
!_LC6_C15 = _LC6_C15~NOT;
_LC6_C15~NOT = LCELL( _EQ117);
  _EQ117 =  _LC2_C19
         #  _LC1_C18
         # !_LC1_C13
         #  _LC2_C18;

-- Node name is ':1302' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ118);
  _EQ118 = !_LC1_C13 & !_LC1_C18 & !_LC2_C18 & !_LC2_C19;

-- Node name is ':1307' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ119);
  _EQ119 = !_LC1_C18 & !_LC2_C18 &  _LC2_C19
         # !_LC1_C13 & !_LC2_C18 &  _LC2_C19
         # !_LC1_C13 &  _LC1_C18 & !_LC2_C18
         #  _LC1_C18 & !_LC2_C18 & !_LC2_C19
         # !_LC1_C18 &  _LC2_C18 & !_LC2_C19;

-- Node name is ':1326' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = LCELL( _EQ120);
  _EQ120 = !_LC1_C18 &  _LC2_C18 & !_LC2_C19
         # !_LC2_C18 &  _LC2_C19;

-- Node name is ':1338' 
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = LCELL( _EQ121);
  _EQ121 = !_LC3_C21 & !_LC6_C15 &  _LC7_C21
         #  _LC2_C15;

-- Node name is ':1371' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ122);
  _EQ122 = !_LC1_C13 & !_LC2_C18 & !_LC2_C19
         # !_LC1_C13 & !_LC1_C18 & !_LC2_C19
         # !_LC1_C13 &  _LC1_C18 & !_LC2_C18;

-- Node name is ':1397' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ123);
  _EQ123 = !_LC1_C13 &  _LC1_C18 & !_LC2_C18 &  _LC2_C19
         # !_LC1_C18 &  _LC2_C18 & !_LC2_C19
         #  _LC1_C13 & !_LC1_C18 & !_LC2_C18 &  _LC2_C19;

-- Node name is ':1404' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ124);
  _EQ124 = !_LC6_C15 &  _LC6_C21
         #  _LC3_C21 & !_LC6_C15
         #  _LC2_C15;

-- Node name is ':1437' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ125);
  _EQ125 = !_LC2_C18 &  _LC2_C19
         #  _LC1_C13 & !_LC2_C18
         # !_LC1_C18 & !_LC2_C19
         # !_LC1_C18 & !_LC2_C18;

-- Node name is ':1460' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ126);
  _EQ126 = !_LC1_C18 &  _LC2_C18 & !_LC2_C19
         #  _LC1_C13 &  _LC1_C18 & !_LC2_C18 &  _LC2_C19;

-- Node name is ':1470' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ127);
  _EQ127 =  _LC7_C15
         #  _LC2_C15
         #  _LC6_C15
         #  _LC8_C15;

-- Node name is ':1496' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = LCELL( _EQ128);
  _EQ128 =  _LC1_C18 & !_LC2_C18 &  _LC2_C19
         # !_LC1_C18 &  _LC2_C18 & !_LC2_C19
         #  _LC1_C13 & !_LC2_C18 &  _LC2_C19;

-- Node name is '~1497~1' 
-- Equation name is '~1497~1', location is LC3_C21, type is buried.
-- synthesized logic cell 
_LC3_C21 = LCELL( _EQ129);
  _EQ129 =  _LC1_C18 & !_LC2_C18 & !_LC2_C19;

-- Node name is ':1503' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ130);
  _EQ130 =  _LC2_C15
         #  _LC3_C21 & !_LC6_C15
         #  _LC5_C21 & !_LC6_C15;



Project Information                               f:\study\vhdl\clock\disp.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,306K