Project Information                              f:\study\vhdl\clock\clock.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/14/2003 12:39:14

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

clock     EPF10K10LC84-4   1      13     0    0         0  %    534      92 %

User Pins:                 1      13     0  



Project Information                              f:\study\vhdl\clock\clock.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 45: File f:\study\vhdl\clock\package.vhd: Undefined (X) values of constant "XXXX" are interpreted as 0
Warning: Line 45: File f:\study\vhdl\clock\package.vhd: Undefined (X) values of constant "XXXX" are interpreted as 0
Warning: Line 66: File f:\study\vhdl\clock\package.vhd: Undefined (X) values of constant "XXXXXXX" are interpreted as 0
Warning: Line 66: File f:\study\vhdl\clock\package.vhd: Undefined (X) values of constant "XXXXXXX" are interpreted as 0
Warning: Line 83: File f:\study\vhdl\clock\package.vhd: Undefined (X) values of constant "XXXXXX" are interpreted as 0
Warning: Line 83: File f:\study\vhdl\clock\package.vhd: Undefined (X) values of constant "XXXXXX" are interpreted as 0
Warning: Node 'EN' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Warning: Node 'SYSRES' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem


Project Information                              f:\study\vhdl\clock\clock.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

clock@1                           CLK
clock@5                           common0
clock@6                           common1
clock@7                           common2
clock@8                           common3
clock@9                           common4
clock@10                          common5
clock@3          ---------        EN
clock@16                          segment0
clock@17                          segment1
clock@18                          segment2
clock@19                          segment3
clock@21                          segment4
clock@22                          segment5
clock@23                          segment6
clock@2          ---------        SYSRES


Project Information                              f:\study\vhdl\clock\clock.rpt

** FILE HIERARCHY **



|cnt10:2|
|cnt10:2|lpm_add_sub:201|
|cnt10:2|lpm_add_sub:201|addcore:adder|
|cnt10:2|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|cnt10:2|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|cnt10:2|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|cnt10:10|
|cnt10:10|lpm_add_sub:201|
|cnt10:10|lpm_add_sub:201|addcore:adder|
|cnt10:10|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|cnt10:10|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|cnt10:10|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|cnt10:16|
|cnt10:16|lpm_add_sub:201|
|cnt10:16|lpm_add_sub:201|addcore:adder|
|cnt10:16|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|cnt10:16|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|cnt10:16|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|cnt10:15|
|cnt10:15|lpm_add_sub:201|
|cnt10:15|lpm_add_sub:201|addcore:adder|
|cnt10:15|lpm_add_sub:201|altshift:result_ext_latency_ffs|
|cnt10:15|lpm_add_sub:201|altshift:carry_ext_latency_ffs|
|cnt10:15|lpm_add_sub:201|altshift:oflow_ext_latency_ffs|
|cnt6:3|
|cnt6:3|lpm_add_sub:196|
|cnt6:3|lpm_add_sub:196|addcore:adder|
|cnt6:3|lpm_add_sub:196|altshift:result_ext_latency_ffs|
|cnt6:3|lpm_add_sub:196|altshift:carry_ext_latency_ffs|
|cnt6:3|lpm_add_sub:196|altshift:oflow_ext_latency_ffs|
|cnt6:17|
|cnt6:17|lpm_add_sub:196|
|cnt6:17|lpm_add_sub:196|addcore:adder|
|cnt6:17|lpm_add_sub:196|altshift:result_ext_latency_ffs|
|cnt6:17|lpm_add_sub:196|altshift:carry_ext_latency_ffs|
|cnt6:17|lpm_add_sub:196|altshift:oflow_ext_latency_ffs|
|disp:4|
|disp:4|lpm_add_sub:229|
|disp:4|lpm_add_sub:229|addcore:adder|
|disp:4|lpm_add_sub:229|altshift:result_ext_latency_ffs|
|disp:4|lpm_add_sub:229|altshift:carry_ext_latency_ffs|
|disp:4|lpm_add_sub:229|altshift:oflow_ext_latency_ffs|
|cnt40000:33|
|cnt40000:33|lpm_add_sub:211|
|cnt40000:33|lpm_add_sub:211|addcore:adder|
|cnt40000:33|lpm_add_sub:211|altshift:result_ext_latency_ffs|
|cnt40000:33|lpm_add_sub:211|altshift:carry_ext_latency_ffs|
|cnt40000:33|lpm_add_sub:211|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                     f:\study\vhdl\clock\clock.rpt
clock

***** Logic for device 'clock' compiled without errors.




Device: EPF10K10LC84-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f



Device-Specific Information:                     f:\study\vhdl\clock\clock.rpt