_EQ030 =  cnt1029 & !_LC3_B16 & !_LC3_B24
         # !cnt1029 &  _LC3_B16 & !_LC3_B24;

-- Node name is ':5' = 'cnt1030' 
-- Equation name is 'cnt1030', location is LC5_B16, type is buried.
cnt1030  = DFFE( _EQ031, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ031 = !cnt1029 &  cnt1030 & !_LC3_B24
         #  cnt1030 & !_LC3_B16 & !_LC3_B24
         #  cnt1029 & !cnt1030 &  _LC3_B16 & !_LC3_B24;

-- Node name is ':4' = 'cnt1031' 
-- Equation name is 'cnt1031', location is LC7_B16, type is buried.
cnt1031  = DFFE( _EQ032, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ032 = !cnt1030 &  cnt1031 & !_LC3_B24
         #  cnt1031 & !_LC3_B24 & !_LC6_B16
         #  cnt1030 & !cnt1031 & !_LC3_B24 &  _LC6_B16;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B24', type is buried 
_LC7_B24 = LCELL( _EQ033);
  _EQ033 =  cnt100 &  cnt101;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:175' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = LCELL( _EQ034);
  _EQ034 =  cnt100 &  cnt101 &  cnt102 &  cnt103;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = LCELL( _EQ035);
  _EQ035 =  cnt104 &  _LC2_B24;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:187' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = LCELL( _EQ036);
  _EQ036 =  cnt104 &  cnt105 &  cnt106 &  _LC2_B24;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = LCELL( _EQ037);
  _EQ037 =  cnt107 &  _LC5_B20;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:199' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ038);
  _EQ038 =  cnt107 &  cnt108 &  cnt109 &  _LC5_B20;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B19', type is buried 
_LC1_B19 = LCELL( _EQ039);
  _EQ039 =  cnt1010 &  _LC1_B20;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:211' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B22', type is buried 
_LC4_B22 = LCELL( _EQ040);
  _EQ040 =  cnt1011 &  cnt1012 &  _LC1_B19;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:219' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B22', type is buried 
_LC1_B22 = LCELL( _EQ041);
  _EQ041 =  cnt1013 &  cnt1014 &  _LC4_B22;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:227' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B17', type is buried 
_LC1_B17 = LCELL( _EQ042);
  _EQ042 =  cnt1015 &  cnt1016 &  _LC1_B22;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:235' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = LCELL( _EQ043);
  _EQ043 =  cnt1017 &  cnt1018 &  _LC1_B17;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:243' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = LCELL( _EQ044);
  _EQ044 =  cnt1019 &  cnt1020 &  _LC4_B17;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:251' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B23', type is buried 
_LC8_B23 = LCELL( _EQ045);
  _EQ045 =  cnt1021 &  cnt1022 &  _LC5_B23;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:255' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = LCELL( _EQ046);
  _EQ046 =  cnt1023 &  _LC8_B23;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:263' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = LCELL( _EQ047);
  _EQ047 =  cnt1023 &  cnt1024 &  cnt1025 &  _LC8_B23;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:267' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ048);
  _EQ048 =  cnt1026 &  _LC1_B18;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:275' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ049);
  _EQ049 =  cnt1027 &  cnt1028 &  _LC5_B18;

-- Node name is '|LPM_ADD_SUB:141|addcore:adder|:279' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B16', type is buried 
_LC6_B16 = LCELL( _EQ050);
  _EQ050 =  cnt1029 &  _LC3_B16;

-- Node name is '~71~1' 
-- Equation name is '~71~1', location is LC7_B20, type is buried.
-- synthesized logic cell 
_LC7_B20 = LCELL( _EQ051);
  _EQ051 =  cnt104
         #  cnt105
         #  cnt106
         #  cnt107;

-- Node name is '~71~2' 
-- Equation name is '~71~2', location is LC4_B24, type is buried.
-- synthesized logic cell 
_LC4_B24 = LCELL( _EQ052);
  _EQ052 =  _LC7_B20
         #  cnt101
         #  cnt102
         # !cnt103;

-- Node name is '~71~3' 
-- Equation name is '~71~3', location is LC3_B23, type is buried.
-- synthesized logic cell 
_LC3_B23 = LCELL( _EQ053);
  _EQ053 =  cnt1020
         #  cnt1021
         #  cnt1022
         #  cnt1023;

-- Node name is '~71~4' 
-- Equation name is '~71~4', location is LC7_B17, type is buried.
-- synthesized logic cell 
_LC7_B17 = LCELL( _EQ054);
  _EQ054 =  cnt1016
         #  cnt1017
         #  cnt1018
         #  cnt1019;

-- Node name is '~71~5' 
-- Equation name is '~71~5', location is LC3_B22, type is buried.
-- synthesized logic cell 
_LC3_B22 = LCELL( _EQ055);
  _EQ055 =  cnt1012
         #  cnt1013
         #  cnt1014
         #  cnt1015;

-- Node name is '~71~6' 
-- Equation name is '~71~6', location is LC2_B22, type is buried.
-- synthesized logic cell 
_LC2_B22 = LCELL( _EQ056);
  _EQ056 =  cnt108
         #  cnt109
         #  cnt1010
         #  cnt1011;

-- Node name is '~71~7' 
-- Equation name is '~71~7', location is LC1_B23, type is buried.
-- synthesized logic cell 
_LC1_B23 = LCELL( _EQ057);
  _EQ057 =  _LC3_B23
         #  _LC7_B17
         #  _LC3_B22
         #  _LC2_B22;

-- Node name is '~71~8' 
-- Equation name is '~71~8', location is LC2_B16, type is buried.
-- synthesized logic cell 
_LC2_B16 = LCELL( _EQ058);
  _EQ058 =  cnt1029
         #  cnt1030
         #  cnt1031;

-- Node name is '~71~9' 
-- Equation name is '~71~9', location is LC8_B18, type is buried.
-- synthesized logic cell 
_LC8_B18 = LCELL( _EQ059);
  _EQ059 =  cnt1025
         #  cnt1026
         #  cnt1027;

-- Node name is '~71~10' 
-- Equation name is '~71~10', location is LC1_B16, type is buried.
-- synthesized logic cell 
_LC1_B16 = LCELL( _EQ060);
  _EQ060 =  cnt1028
         #  _LC2_B16
         #  cnt1024
         #  _LC8_B18;

-- Node name is ':71' 
-- Equation name is '_LC3_B24', type is buried 
!_LC3_B24 = _LC3_B24~NOT;
_LC3_B24~NOT = LCELL( _EQ061);
  _EQ061 = !cnt100
         #  _LC4_B24
         #  _LC1_B23
         #  _LC1_B16;



Project Information                              f:\study\vhdl\clock\div10.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,298K