;******************************************************************************
;               		SJTU DSP Tech. Center
;        Copyright (c) 2001 SJTU DSP Tech. Center. All Rights Reserved.
;
;  Description:
;  		TMS320C54x Program for Students Experiment
;
;  History:
;		Date		Authors				Changes
;		2003/07/23	Zheng Yigang		Created
;******************************************************************************
STACK_ADDR		.set		0x0500
    .mmregs
    .global main
;==========================================================================
    .bss    x, 1
    .bss    y, 1
    .bss    z, 1
    .bss    ww, 1
    
	.text
main:
    ssbx	INTM
    stm     #STACK_ADDR, SP     ;set stack address
 	stm		#0x00a0, PMST		;set Processor mode status register
	stm		#0x0000, SWWSR      ;set soft wait-state register
	
	stm		#0x0009, IMR		;enable TINT and INT0
	stm		#0xffff, IFR		;clear all pending int

	stm     #0x8, PRD           ;set time interrupt calling period
	stm     #0x0015, TCR        ;set time control register,and stop the timer
	
	sub		A
	stl		A, *(x)			;clear x,y,z
	stl		A, *(y)	
	stl		A, *(z)	
	stl     A, *(ww)
;===================================================================
;*********   to test time interbreak          *********************=
;===================================================================
	rsbx    INTM                ;enable global INT
	stm     #0x0025, TCR	    ;start timer
	
	stm		#2, AR5
loop_timer_int:
	nop
	nop
	banz	loop_timer_int, *AR5-

;==================================================================
;***********   to test soft interbreak     ************************
;***********  and to compare the differ between intr and trap     
;==================================================================
;	rsbx	INTM
	intr    2                   ;call sint17,y++
    stm		#20-1, AR5
loop_intr_int:
	nop
	nop
	banz	loop_intr_int, *AR5-
	
;	rsbx    INTM
	trap    3					;call sint18, z++
    stm		#20-1, AR5
loop_trap_int:
	nop
	nop
	banz	loop_trap_int, *AR5-
;==================================================================
;********   the dead loop of the program    **********************8
;==================================================================	
dead_loop:
	nop
    nop
    nop
    b		dead_loop
;------------------------------------------------------------------------------
;==============================================================================
INT0_ISR:
	;add code here
	ld      *(ww),A
	add     #1,A
	stl     A,*(ww)
	popm	ST1
	popm	ST0
	rete

SINT17_ISR:
	ld		*(y), A
	add		#1, A
	stl		A, *(y)
			
	popm	ST1
	popm	ST0
	rete
	
SINT18_ISR:
	;add code here
	ld		*(z), A
	add		#1, A
	stl		A, *(z)
	
	popm	ST1
	popm	ST0
	ret
	
TINT_ISR:
    ld		*(x), A
	add		#1, A
	stl		A, *(x)
	
	popm	ST1
	popm	ST0
	rete
	
INT3_ISR:
	;add code here
		
	popm	ST1
	popm	ST0
	rete
;===============================================================================
;               redefine the interrupte vectors                                ;
;===============================================================================
    .sect	"vectors"
int_RESET:
	b		main
	nop
	nop

	.space	4*16

int_SINT17:
	bd		SINT17_ISR
	pshm	ST0
	pshm	ST1
	
int_SINT18:
	bd		SINT18_ISR
	pshm	ST0
	pshm	ST1

	.space	48*16
	
int_SINT0:
	bd	    INT0_ISR
	pshm	ST0
	pshm	ST1

	.space	8*16
	
int_TINT:
    bd      TINT_ISR
    pshm	ST0
	pshm	ST1

    .space  16*16
    
int_INT3:
   	bd		INT3_ISR
   	pshm	ST0
   	pshm	ST1

   	.space	28*16

;end of interrupt.s54