/* set PMST to: MP =  OVLY = 1; DROM off, CLKOUT on */
#define PMST            0x1d    
#define PMST_VAL        0xffe0  

/* set wait-state control reg for: 2 w/s or more on i/o; one for ext memory */
#define SWWSR           0x28
#define SWWSR_VAL       0x0209  

/* set external-banks switch control for: no bank switching; BH set */
#define BSCR            0x29
#define BSCR_VAL        0x02

/* Set Default Reset Initialization Value */
#define    ZEROS        0x0000

/* Set Peripheral Control Register Addresses for DEV_RESET */
#define IFR             0x0001

#define DMPREC          0x0054
#define DMSA            0x0055
#define DMSDI           0x0056

#define DMA_CH0_DMFSC_SUB_ADDR  0x0003
#define DMA_CH1_DMFSC_SUB_ADDR  0x0008
#define DMA_CH2_DMFSC_SUB_ADDR  0x000D
#define DMA_CH3_DMFSC_SUB_ADDR  0x0012
#define DMA_CH4_DMFSC_SUB_ADDR  0x0017
#define DMA_CH5_DMFSC_SUB_ADDR  0x001c


#define MCBSP0_SPSA     0x0038
#define MCBSP0_SPSD     0x0039
#define MCBSP1_SPSA     0x0048
#define MCBSP1_SPSD     0x0049

#define MCBSP2_SPSA     0x0034
#define MCBSP2_SPSD     0x0035

#define MCBSP_SPCR1_SUB_ADDR   0x0000
#define MCBSP_SPCR2_SUB_ADDR   0x0001
#define MCBSP_SRGR1_SUB_ADDR   0x0006
#define MCBSP_SRGR2_SUB_ADDR   0x0007
#define MCBSP_MCR1_SUB_ADDR    0x0008
#define MCBSP_MCR2_SUB_ADDR    0x0009
#define SRGR1_INIT             0x0001

#define PRD0            0x0025
#define TCR0            0x0026

#define PRD1            0x0031
#define TCR1            0x0032

#define TIMER_STOP             0x0010
#define TIMER_RESET            0x0020 
#define PRD_DEFAULT            0xFFFF     

#define GPIOCR                 0x0010
 



/* The Startup() function is executed when the GEL file is loaded. */

StartUp()
{
	GEL_Reset(); 
}

menuitem "C54x";
hotmenu C54x_CPU_Reset()
{
	GEL_Reset();
/*	GEL_MapReset(); */
/*	GEL_MapOff(); */
	*(int *)PMST = PMST_VAL;
	*(int *)SWWSR = SWWSR_VAL;
	*(int *)BSCR = BSCR_VAL;
}

hotmenu C5402_Init()
{
	C54x_CPU_Reset();
	C5402_Periph_Reset();
	GEL_MapOn();
	GEL_MapReset();

	GEL_XMDef(0,0x1e,1,0x8000,0x7f);
	GEL_XMOn();
	GEL_MapAdd(0x80,0,0x80,1,1);      	/* Vectors */
	GEL_MapAdd(0x1000,0,0x1000,1,1);	/* Program */

	GEL_MapAdd(0x0,1,0x60,1,1);			/* MMRs */
	GEL_MapAdd(0x100,1,0x400,1,1);	    /* Stack */
	GEL_MapAdd(0x2000,1,0x1000,1,1);	/* Data */
}

hotmenu C5402_DSK_Init()
{
	C54x_CPU_Reset();
	C5402_Periph_Reset();
	GEL_MapOn();
	GEL_MapReset();

	GEL_XMDef(0,0x1e,1,0x8000,0x7f);
	GEL_XMOn();
	GEL_MapAdd(0x80,0,0x3F80,1,1);		/* DARAM */
	GEL_MapAdd(0x4000,0,0xC000,1,1);	/* External */
	GEL_MapAdd(0x18000,0,0x8000,1,1);	/* Extended Addressing - Page 0 */

	GEL_MapAdd(0x0,1,0x60,1,1);			/* MMRs */
	GEL_MapAdd(0x60,1,0x3FA0,1,1);		/* DARAM */
	GEL_MapAdd(0x4000,1,0xC000,1,1);	/* External */

	GEL_MapAdd(0x0,2,0x6,1,1);			/* I/O space */

	*(int *)0x4@io = 0xff03;			/* Enable SRAM */
}

/* ****************************** */

C5402_Periph_Reset()
{
	*(int *)IFR = 0xFFFF;  

	DMA_Reset();
	MCBSP0_Reset();
	MCBSP1_Reset();
	TIMER0_Reset();
	TIMER1_Reset();
    GPIO_Reset();
}


DMA_Reset()
{
	*(int *)DMPREC = ZEROS;  
    
	*(int *)DMSA = DMA_CH0_DMFSC_SUB_ADDR;
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSA  = DMA_CH1_DMFSC_SUB_ADDR;
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSDI = ZEROS;    
 
	*(int *)DMSA  = DMA_CH2_DMFSC_SUB_ADDR;
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSDI = ZEROS;     
 
	*(int *)DMSA  = DMA_CH3_DMFSC_SUB_ADDR;
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSDI = ZEROS;     
 
	*(int *)DMSA  = DMA_CH4_DMFSC_SUB_ADDR;
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSDI = ZEROS;    
 
	*(int *)DMSA  = DMA_CH2_DMFSC_SUB_ADDR;
	*(int *)DMSDI = ZEROS;     
	*(int *)DMSDI = ZEROS;     
}

MCBSP0_Reset()
{
	*(int *)MCBSP0_SPSA = MCBSP_SPCR1_SUB_ADDR;    
	*(int *)MCBSP0_SPSD = ZEROS;                   
	*(int *)MCBSP0_SPSA = MCBSP_SPCR2_SUB_ADDR;    
	*(int *)MCBSP0_SPSD = ZEROS; 
                 
	*(int *)MCBSP0_SPSA = MCBSP_SRGR1_SUB_ADDR;    
	*(int *)MCBSP0_SPSD = SRGR1_INIT;              
	*(int *)MCBSP0_SPSA = MCBSP_SRGR2_SUB_ADDR;    
	*(int *)MCBSP0_SPSD = ZEROS;                   

	*(int *)MCBSP0_SPSA = MCBSP_MCR1_SUB_ADDR;     
	*(int *)MCBSP0_SPSD = ZEROS;                   
	*(int *)MCBSP0_SPSA = MCBSP_MCR2_SUB_ADDR;     
	*(int *)MCBSP0_SPSD = ZEROS;                   
}

MCBSP1_Reset()
{
	*(int *)MCBSP1_SPSA = MCBSP_SPCR1_SUB_ADDR;   
	*(int *)MCBSP1_SPSD = ZEROS;                   
	*(int *)MCBSP1_SPSA = MCBSP_SPCR2_SUB_ADDR;    
	*(int *)MCBSP1_SPSD = ZEROS;                   

	*(int *)MCBSP1_SPSA = MCBSP_SRGR1_SUB_ADDR;    
	*(int *)MCBSP1_SPSD = SRGR1_INIT;              
	*(int *)MCBSP1_SPSA = MCBSP_SRGR2_SUB_ADDR;    
	*(int *)MCBSP1_SPSD = ZEROS;   
                
	*(int *)MCBSP1_SPSA = MCBSP_MCR1_SUB_ADDR;     
	*(int *)MCBSP1_SPSD = ZEROS;                   
	*(int *)MCBSP1_SPSA = MCBSP_MCR2_SUB_ADDR;     
	*(int *)MCBSP1_SPSD = ZEROS;
}   

MCBSP2_Reset()
{
	*(int *)MCBSP2_SPSA = MCBSP_SPCR1_SUB_ADDR;   
	*(int *)MCBSP2_SPSD = ZEROS;                   
	*(int *)MCBSP2_SPSA = MCBSP_SPCR2_SUB_ADDR;    
	*(int *)MCBSP2_SPSD = ZEROS;
                   
	*(int *)MCBSP2_SPSA = MCBSP_SRGR1_SUB_ADDR;    
	*(int *)MCBSP2_SPSD = SRGR1_INIT;              
	*(int *)MCBSP2_SPSA = MCBSP_SRGR2_SUB_ADDR;    
	*(int *)MCBSP2_SPSD = ZEROS;   
                
	*(int *)MCBSP2_SPSA = MCBSP_MCR1_SUB_ADDR;     
	*(int *)MCBSP2_SPSD = ZEROS;                   
	*(int *)MCBSP2_SPSA = MCBSP_MCR2_SUB_ADDR;     
	*(int *)MCBSP2_SPSD = ZEROS;
}   

TIMER0_Reset()
{
	*(int *)TCR0 = TIMER_STOP;              
	*(int *)PRD0 = PRD_DEFAULT;              
	*(int *)TCR0 = TIMER_RESET;
}

TIMER1_Reset()
{     

	*(int *)TCR1 = TIMER_STOP;               
	*(int *)PRD1 = PRD_DEFAULT;              
	*(int *)TCR1 = TIMER_RESET;              
}  

GPIO_Reset()
{
	*(int *)GPIOCR = ZEROS;
}