;******************************************************************************
;               		SJTU DSP Tech. Center
;        Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
;  History:
;		Date		Authors			Changes
;		2003/08/30	Xu Sheng		Created.
;******************************************************************************
	.mmregs
;=================== DMA register address============================
DMPREC			.set		0x54
DMSA			.set		0x55
DMSDI			.set		0x56
	
;**************************constants*******************************************
DATA_STORE_SIZE		.set	16
STACK_ADDR			.set	0x0500
;******************************************************************************

;************************memory allocation*************************************
	.bss	src_buf, DATA_STORE_SIZE
	.bss	dst_buf, DATA_STORE_SIZE
	.bss	tmp_var, 1
	.bss	dma0_int_flag, 1
;******************************************************************************

;**************************functions*******************************************
	.global  	main
	.global   	DSPInit
;******************************************************************************

	.text
;******************************************************************************
;** Function:	main
;** Description:	Main program
;******************************************************************************
main:
	stm		#STACK_ADDR, SP

	;DSP initialization (inluding settings of CPLD, DMA and McBSP )
	call	DSPInit

	;LED0 shines to show that all initializations have finished
	portr	#0, *(tmp_var)
	orm		#0x0001, *(tmp_var)
	portw	*(tmp_var), #0
	
	sub		A
	;initialize src_buf
	stm		#src_buf, AR2
	ld		#1, B
	stm		#DATA_STORE_SIZE-1, BRC
	rptb	ini_src_loop-1
	stl		A, *AR2+
	add		B, A
ini_src_loop:
	
	;set DMA0, DMA4 high priority, 中斷復(fù)用INTOSEL=10b(DMA1,2,3), close all other DMA
	stm		#0x1180, DMPREC

;========================================
;	use DMA 0 transfer, both src and dst are contiguous
;	poll the register to know the end of the transfer
	stm		#DMA_CNST0, AR3
	stm		#0, DMSA
	stm		#DMSDI, AR2				;帶地址自動(dòng)增加得子區(qū)訪問(wèn)寄存器
	rpt		#40-1
	mvdd	*AR3+, *AR2
	
	;enable DMA 0
	orm		#0x0001, *(DMPREC)
poll_loop:
	ldm		DMPREC, A
	and		#0x0001, A 
	bc		poll_loop, ANEQ	
	
;========================================
;	set DMA 0 transfer, src and dst are modified with different
;	index, use interrupt to notify CPU
	
	;ready for data receive
	stm		#0x0040, IMR				;set IMR to enable DMA0 Interrupt
	stm		#0xffff, IFR				;set IFR to clear pending interrupt
	
	stm		#DMA_CNST1, AR3
	stm		#0, DMSA
	stm		#DMSDI, AR2				;帶地址自動(dòng)增加得子區(qū)訪問(wèn)寄存器
	rpt		#40-1
	mvdd	*AR3+, *AR2

	;enable DMA 0
	rsbx	INTM
	orm		#0x0001, *(DMPREC)
	
	;wait for DMA transfer stop
	st		#0, *(dma0_int_flag)
wait_dma_loop:
	ld		*(dma0_int_flag), A
	nop
	nop
	bc		wait_dma_loop, AEQ
	
dead_loop:
	nop
	nop
	nop
	b		dead_loop
	
;**************************vectors*********************************************
   	.sect   "vectors"
int_reset:
	b      	main        ;Main program
    nop
    nop

   .space	84*16

int_damc0:
	orm		#1, *(dma0_int_flag)
	rete

	.space	33*16


;============================================================
	.sect	"DMA_tst_table"
DMA_CNST0:
	.word	src_buf	;DMSRC0
	.word	dst_buf	;DMDST0 通道0目的地址
	.word	DATA_STORE_SIZE-1		;DMCTR0 元素?cái)?shù)目-1
	.word	0x0000	;DMSFC0 
					;DSYN=0000, DBLW=0(單字模式), Frame Count=1-1
	.word	0x0145	;DMMCR0
					;AUTOINIT=0(自動(dòng)初始化), DINM=0, IMOD=0(幀結(jié)束中斷), 
					;CTMOD=0(多幀模式), SIND=001(不修改源地址), DMS=01(數(shù)據(jù)空間),
					;DIND=001(目的地址加1), DMD=01(數(shù)據(jù)空間)

	.word	0		;DMSRC1
	.word	0		;DMDST1
	.word	0		;DMCTR1
	.word	0		;DMSFC1
	.word	0		;DMMCR1

	.word	0		;DMSRC2
	.word	0		;DMDST2
	.word	0		;DMCTR2
	.word	0		;DMSFC2
	.word	0		;DMMCR2

	.word	0		;DMSRC3
	.word	0		;DMDST3
	.word	0		;DMCTR3
	.word	0		;DMSFC3
	.word	0		;DMMCR3

	.word	0		;DMSRC4
	.word	0		;DMDST4
	.word	0		;DMCTR4
	.word	0		;DMSFC4
	.word	0		;DMMCR4

	.word	0		;DMSRC5
	.word	0		;DMDST5
	.word	0		;DMCTR5
	.word	0		;DMSFC5
	.word	0		;DMMCR5

	.word	0		;DMSRCP, no extended addressing
	.word	0		;DMDSTP, no extended addressing

	.word	0		;DMIDX0
	.word	0		;DMIDX1

	.word	0		;DMFRI0
	.word	0		;DMFRI1

	.word	0		;DMGSA(重載源地址)
	.word	0		;DMGDA(重載目的地址)
	.word	0		;DMGCR(重載元素?cái)?shù)目-1)
	.word	0		;DMGFR(重載幀數(shù)目-1)

DMA_CNST1:
	.word	src_buf	;DMSRC0
	.word	dst_buf	;DMDST0 通道0目的地址
	.word	DATA_STORE_SIZE/4-1		;DMCTR0 元素?cái)?shù)目-1
	.word	0x0003	;DMSFC0 
					;DSYN=0000, DBLW=0(單字模式), Frame Count=4-1
	.word	0x4155	;DMMCR0
					;AUTOINIT=0(自動(dòng)初始化), DINM=1, IMOD=0(幀結(jié)束中斷), 
					;CTMOD=0(多幀模式), SIND=001(不修改源地址), DMS=01(數(shù)據(jù)空間),
					;DIND=101(目的地址加1), DMD=01(數(shù)據(jù)空間)

	.word	0		;DMSRC1
	.word	0		;DMDST1
	.word	0		;DMCTR1
	.word	0		;DMSFC1
	.word	0		;DMMCR1

	.word	0		;DMSRC2
	.word	0		;DMDST2
	.word	0		;DMCTR2
	.word	0		;DMSFC2
	.word	0		;DMMCR2

	.word	0		;DMSRC3
	.word	0		;DMDST3
	.word	0		;DMCTR3
	.word	0		;DMSFC3
	.word	0		;DMMCR3

	.word	0		;DMSRC4
	.word	0		;DMDST4
	.word	0		;DMCTR4
	.word	0		;DMSFC4
	.word	0		;DMMCR4

	.word	0		;DMSRC5
	.word	0		;DMDST5
	.word	0		;DMCTR5
	.word	0		;DMSFC5
	.word	0		;DMMCR5

	.word	0		;DMSRCP, no extended addressing
	.word	0		;DMDSTP, no extended addressing

	.word	4		;DMIDX0
	.word	0		;DMIDX1

	.word	-(3*4-1)		;DMFRI0
	.word	0		;DMFRI1

	.word	0		;DMGSA(重載源地址)
	.word	0		;DMGDA(重載目的地址)
	.word	0		;DMGCR(重載元素?cái)?shù)目-1)
	.word	0		;DMGFR(重載幀數(shù)目-1)