?? regs.h
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/******************************************************************/
/* regs.h V0.00 */
/* Copyright (c) Texas Instruments , Incorporated 2000 */
/******************************************************************/
/******************************************************************/
/* DEFINE ALL PERIPHERAL MEMORY MAPPED REGISTER ADRESSES */
/******************************************************************/
/******************************************************************/
/* Check to see if mmregs.h has been previously included by */
/* another header, if so, skip this and go on */
/******************************************************************/
#if !defined(__MMREGS)
#include <limits.h>
/******************************************************************/
/* Target specific data and macros */
/* */
/* MASK_TARGET_WORD - bit pattern to mask all bits in a target */
/* word */
/* WORD_SIZE - size in bits of target word */
/* BASE_ADDR - base address of memory-mapped peripheral */
/* control registers */
/******************************************************************/
#define MASK_TARGET_WORD 0xffff
#define TARGET_WRD_SZ CHAR_BIT
#define BYTES_PER_WORD TARGET_WRD_SZ/8
#define WORD_SIZE (CHAR_BIT * sizeof(unsigned int))
#define SP_ADDR(port) (0x22 + (0x10 * port))
#define DRR_ADDR(port) (0x20 + (0x10 * port))
#define DXR_ADDR(port) (0x21 + (0x10 * port))
#define BSP_ADDR(port) (0x22 + (0x20 * port))
#define BDRR_ADDR(port) (0x20 + (0x20 * port))
#define BDXR_ADDR(port) (0x21 + (0x20 * port))
#define BSPCE_ADDR(port) (0x23 + (0x20 * port))
#define AXR_ADDR(port) (0x38 + (0x04 * port))
#define ARR_ADDR(port) (0x3a + (0x04 * port))
#define TDM_ADDR TSPC
#define TIMER_ADDR TCR_ADDR
/*----------------------------------------------------------------------------*/
/* MACRO FUNCTIONS */
/*----------------------------------------------------------------------------*/
/******************************************************************/
/* Define data structures for all memory mapped registers */
/******************************************************************/
/*----------------------------------------------------------------*/
/* Define bit fields for Serial Port Control Registers */
/*----------------------------------------------------------------*/
#define RSRFULL 13
#define RSRFULL_SZ 1
#define XSREMPTY 12
#define XSREMPTY_SZ 1
#define IN1 9
#define IN1_SZ 1
#define IN0 8
#define IN0_SZ 1
#define TXM 5
#define TXM_SZ 1
#define MCM 4
#define MCM_SZ 1
#define FSM 3
#define FSM_SZ 1
#define FO 2
#define FO_SZ 1
#define TDM 0
#define TDM_SZ 1
#define CLKDV 0
#define CLKDV_SZ 5
#define FSP 5
#define FSP_SZ 1
#define CLKP 6
#define CLKP_SZ 1
#define FE 7
#define FE_SZ 1
#define FIG 8
#define FIG_SZ 1
#define PCM 9
#define PCM_SZ 1
#define BXE 10
#define BXE_SZ 1
#define XH 11
#define XH_SZ 1
#define HALTX 12
#define HALTX_SZ 1
#define BRE 13
#define BRE_SZ 1
#define RH 14
#define RH_SZ 1
#define HALTR 15
#define HALTR_SZ 1
/******************************************************************/
/* Define Timer Period, and Control Registers with all related */
/* data structures, macros, and functions */
/*----------------------------------------------------------------*/
#define PSC 6
#define PSC_SZ 4
#define TRB 5
#define TRB_SZ 1
#define TSS 4
#define TSS_SZ 1
#define TDDR 0
#define TDDR_SZ 4
/*---------------------------------------------------------------*/
/* Data structures, macros for Clock Mode Register */
/*---------------------------------------------------------------*/
#define PLLMUL 12
#define PLLMUL_SZ 4
#define PLLDIV 11
#define PLLDIV_SZ 1
#define PLLCOUNT 3
#define PLLCOUNT_SZ 8
#define PLLON_OFF 2
#define PLLON_OFF_SZ 1
#define PLLNDIV 1
#define PLLNDIV_SZ 1
#define PLLSTATUS 0
#define PLLSTATUS_SZ 1
/******************************************************************/
/* Define bit fields for Software Wait State Register */
/******************************************************************/
#define IO 12
#define IO_SZ 3
#define DATA_HI 9
#define DATA_HI_SZ 3
#define DATA_LO 6
#define DATA_LO_SZ 3
#define PROGRAM_HI 3
#define PROGRAM_HI_SZ 3
#define PROGRAM_LO 0
#define PROGRAM_LO_SZ 3
/*-------------------------------------------------------------------*/
/* Define structure for Bank Switch Control Register */
/*-------------------------------------------------------------------*/
#define BNKCMP 12
#define BNKCMP_SZ 4
#define PSDS 11
#define PSDS_SZ 1
#define BH 1
#define BH_SZ 1
#define EXIO 0
#define EXIO_SZ 1
#define INT0 0
#define INT1 1
#define INT2 2
#define TINT 3
#define RINT0 4
#define XINT0 5
#define RINT2 6
#define XINT2 7
#define INT3 8
#define HPINT 9
#define RINT1 10
#define XINT1 11
#define DMAC0 6
#define DMAC1 7
#define DMAC2 10
#define DMAC3 11
#define DMAC4 12
#define DMAC5 13
/***************************************************************/
/* DEFINE DATA STRUCTURE FOR HOST PORT INTERFACE CONTROL REG */
/***************************************************************/
#define BOB 0
#define SMOD 1
#define DSPINT 2
#define HINT 3
/******************************************************************/
/* Serial Port 0 defined for C541 only */
/******************************************************************/
#define DRR0 *(volatile unsigned int *)0x20
#define DRR0_ADDR 0x20
#define DXR0 *(volatile unsigned int *)0x21
#define DXR0_ADDR 0x21
#define SPC0 *(volatile unsigned int *)0x22
#define SPC0_ADDR 0x22
/******************************************************************/
/* Buffered Serial Port 0 defined for all devices except C541 */
/******************************************************************/
#define BSPC0 *(volatile unsigned int *)0x22
#define BSPC0_ADDR 0x22
#define BSPCE0 *(volatile unsigned int *)0x23
#define BSPCE0_ADDR 0x23
#define BDRR0 *(volatile unsigned int *)0x20
#define BDRR0_ADDR 0x20
#define BDXR0 *(volatile unsigned int *)0x21
#define BDXR0_ADDR 0x21
/*********************************************************************/
/* Defined flags for use in setting control for HPI host interface */
/* control pins */
/* The value of these constants is their relative bit position in */
/* the control structure for the host side of the HPI interface */
/*********************************************************************/
#define HAS_PIN 0
#define HBIL_PIN 1
#define HCNTL0_PIN 2
#define HCNTL1_PIN 3
#define HCS_PIN 4
#define HD0_PIN 5
#define HDS1_PIN 6
#define HDS2_PIN 7
#define HINT_PIN 8
#define HRDY_PIN 9
#define HRW_PIN 10
/*********************************************************************/
/* AUTOBUFFERING UNIT (Buffered Serial Port 0) */
/* Defined for all except C541 */
/*********************************************************************/
#define AXR0 *(volatile unsigned int *)0x38
#define AXR0_ADDR 0x38
#define BKX0 *(volatile unsigned int *)0x39
#define BKX0_ADDR 0x39
#define ARR0 *(volatile unsigned int *)0x3a
#define ARR0_ADDR 0x3a
#define BKR0 *(volatile unsigned int *)0x3b
#define BKR0_ADDR 0x3b
/*********************************************************************/
/* AUTOBUFFERING UNIT (Buffered Serial Port 1) */
/* Defined for C548 Only!!!!!! */
/*********************************************************************/
#define AXR1 *(volatile unsigned int *)0x3c
#define AXR1_ADDR 0x3c
#define BKX1 *(volatile unsigned int *)0x3d
#define BKX1_ADDR 0x3d
#define ARR1 *(volatile unsigned int *)0x3e
#define ARR1_ADDR 0x3e
#define BKR1 *(volatile unsigned int *)0x3f
#define BKR1_ADDR 0x3f
/*********************************************************************/
/* Buffered Serial Port 1 defined only for C548 */
/*********************************************************************/
#define BSPC1 *(volatile unsigned int *)0x42
#define BSPC1_ADDR 0x42
#define BSPCE1 *(volatile unsigned int *)0x43
#define BSPCE1_ADDR 0x43
#define BDRR1 *(volatile unsigned int *)0x40
#define BDDR1_ADDR 0x40
#define BDXR1 *(volatile unsigned int *)0x41
#define BDXR1_ADDR 0x41
#define __MMREGS
#endif
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