Release 6.1i - xst G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> Reading design: can_fifo.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : can_fifo.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : can_fifoOutput Format                      : NGCTarget Device                      : xc2s300e-6-pq208---- Source OptionsTop Module Name                    : can_fifoAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : can_fifo.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NO=========================================================================WARNING:Xst:1885 - LSO file is empty, default list of libraries is used=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "can_fifo.v"Compiling include file "can_defines.v"Module <can_fifo> compiledNo errors in compilationAnalysis of file <can_fifo.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <can_fifo>.WARNING:Xst:916 - can_fifo.v line 182: Delay is ignored for synthesis.WARNING:Xst:916 - can_fifo.v line 184: Delay is ignored for synthesis.WARNING:Xst:916 - can_fifo.v line 194: Delay is ignored for synthesis.WARNING:Xst:916 - can_fifo.v line 196: Delay is ignored for synthesis.WARNING:Xst:916 - can_fifo.v line 206: Delay is ignored for synthesis.WARNING:Xst:915 - Message (916) is reported only 5 times for each module.Module <can_fifo> is correct for synthesis. Analyzing module <RAMB4_S8_S8>.Analyzing module <RAMB4_S4_S4>.Analyzing module <RAMB4_S1_S1>.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <can_fifo>.    Related source file is can_fifo.v.WARNING:Xst:647 - Input <addr<7:6>> is never used.WARNING:Xst:647 - Input <fifo_selected> is never used.    Found 7-bit updown counter for signal <info_cnt>.    Found 6-bit subtractor for signal <$n0019>.    Found 7-bit addsub for signal <$n0020>.    Found 7-bit subtractor for signal <$n0030> created at line 271.    Found 6-bit adder for signal <$n0032> created at line 231.    Found 1-bit xor2 for signal <$n0056> created at line 285.    Found 7-bit register for signal <fifo_cnt>.    Found 1-bit register for signal <latch_overrun>.    Found 4-bit up counter for signal <len_cnt>.    Found 6-bit up counter for signal <rd_info_pointer>.    Found 6-bit register for signal <rd_pointer>.    Found 6-bit adder for signal <read_address>.    Found 6-bit up counter for signal <wr_info_pointer>.    Found 6-bit up counter for signal <wr_pointer>.    Found 1-bit register for signal <wr_q>.    Found 7 1-bit 2-to-1 multiplexers.    Summary:	inferred   5 Counter(s).	inferred  15 D-type flip-flop(s).	inferred   5 Adder/Subtracter(s).	inferred   7 Multiplexer(s).Unit <can_fifo> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 4  1-bit register                   : 2  6-bit register                   : 1  7-bit register                   : 1# Counters                         : 5  4-bit up counter                 : 1  6-bit up counter                 : 3  7-bit updown counter             : 1# Multiplexers                     : 1  2-to-1 multiplexer               : 1# Adders/Subtractors               : 5  6-bit adder                      : 2  6-bit subtractor                 : 1  7-bit addsub                     : 1  7-bit subtractor                 : 1# Xors                             : 1  1-bit xor2                       : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <can_fifo> ...Loading device for application Xst from file '2s300e.nph' in environment C:/Program Files/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block can_fifo, actual ratio is 2.