?? can_testbench.v
字號:
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID 5
send_bit(1); // RTR
send_bit(0); // r1
send_bit(0); // r0
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC 4
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(1); // CRC d
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC 3
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC 9
send_bit(1); // CRC DELIM
send_bit(0); // ACK
send_bit(1); // ACK DELIM
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // INTER
end // repeat
end
join
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
// Read irq register
#1 read_register(8'd3);
// Read error code capture register
read_register(8'd12);
// Read error capture code register
// read_register(8'd12);
#4000000;
end
endtask // manual_frame_ext
task bus_off_test; // Testbench sends a frame
begin
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
write_register(8'd12, 8'h00); // data byte 1
write_register(8'd13, 8'h00); // data byte 2
write_register(8'd14, 8'h00); // data byte 3
write_register(8'd15, 8'h00); // data byte 4
write_register(8'd16, 8'h00); // data byte 5
write_register(8'd17, 8'h00); // data byte 6
write_register(8'd18, 8'h00); // data byte 7
write_register(8'd19, 8'h00); // data byte 8
fork
begin
tx_request_command;
end
begin
#2000;
repeat (16)
begin
send_bit(0); // SOF
send_bit(1); // ID
send_bit(1); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // RTR
send_bit(0); // IDE
send_bit(0); // r0
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC DELIM
send_bit(1); // ACK ack error
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // INTER
end // repeat
// Node is error passive now.
// Read irq register (error interrupt should be cleared now.
read_register(8'd3);
repeat (20)
begin
send_bit(0); // SOF
send_bit(1); // ID
send_bit(1); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // RTR
send_bit(0); // IDE
send_bit(0); // r0
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC DELIM
send_bit(1); // ACK ack error
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(0); // ERROR
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // ERROR DELIM
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
send_bit(1); // SUSPEND
end // repeat
// Node is bus-off now
// Read irq register (error interrupt should be cleared now.
read_register(8'd3);
#100000;
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
repeat (64 * 11)
begin
send_bit(1);
end // repeat
// Read irq register (error interrupt should be cleared now.
read_register(8'd3);
repeat (64 * 11)
begin
send_bit(1);
end // repeat
// Read irq register (error interrupt should be cleared now.
read_register(8'd3);
end
join
fork
begin
tx_request_command;
end
begin
#1100;
send_bit(1); // To spend some time before transmitter is ready.
repeat (1)
begin
send_bit(0); // SOF
send_bit(1); // ID
send_bit(1); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(0); // ID
send_bit(1); // ID
send_bit(1); // RTR
send_bit(0); // IDE
send_bit(0); // r0
send_bit(0); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // DLC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(0); // CRC
send_bit(0); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC
send_bit(1); // CRC DELIM
send_bit(0); // ACK
send_bit(1); // ACK DELIM
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // EOF
send_bit(1); // INTER
send_bit(1); // INTER
send_bit(1); // INTER
end // repeat
end
join
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
#4000000;
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
#1000000;
end
endtask // bus_off_test
task send_frame_basic; // CAN IP core sends frames
begin
write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
write_register(8'd12, 8'h56); // data byte 1
write_register(8'd13, 8'h78); // data byte 2
write_register(8'd14, 8'h9a); // data byte 3
write_register(8'd15, 8'hbc); // data byte 4
write_register(8'd16, 8'hde); // data byte 5
write_register(8'd17, 8'hf0); // data byte 6
write_register(8'd18, 8'h0f); // data byte 7
write_register(8'd19, 8'hed); // data byte 8
// Enable irqs (basic mode)
write_register(8'd0, 8'h1e);
fork
begin
#1500;
$display("\n\nStart receiving data from CAN bus");
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
end
begin
tx_request_command;
end
begin
// Transmitting acknowledge
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
#1 rx = 0;
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
#1 rx = 1;
end
join
read_receive_buffer;
release_rx_buffer_command;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
release_rx_buffer_command;
read_receive_buffer;
#200000;
read_receive_buffer;
// Read irq register
read_register(8'd3);
#1000;
end
endtask // send_frame_basic
task send_frame_extended; // CAN IP core sends basic or extended frames in extended mode
begin
// Switch-on reset mode
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
// Set Clock Divider register
extended_mode = 1'b1;
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
// Set Acceptance Code and Acceptance Mask registers
write_register(8'd16, 8'ha6); // acceptance code 0
write_register(8'd17, 8'hb0); // acceptance code 1
write_register(8'd18, 8'h12); // acceptance code 2
write_register(8'd19, 8'h30); // acceptance code 3
write_register(8'd20, 8'h00); // acceptance mask 0
write_register(8'd21, 8'h00); // acceptance mask 1
write_register(8'd22, 8'h00); // acceptance mask 2
write_register(8'd23, 8'h00); // acceptance mask 3
// Switch-off reset mode
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
// After exiting the reset mode sending bus free
repeat (11) send_bit(1);
/* Basic frame format
// Writing TX frame information + identifier + data
write_register(8'd16, 8'h45); // Frame format = 0, Remote transmision request = 1, DLC = 5
write_register(8'd17, 8'ha6); // ID[28:21] = a6
write_register(8'd18, 8'ha0); // ID[20:18] = 5
// write_register(8'd19, 8'h78); RTR does not send any data
// write_register(8'd20, 8'h9a);
// write_register(8'd21, 8'hbc);
// write_register(8'd22, 8'hde);
// write_register(8'd23, 8'hf0);
// write_register(8'd24, 8'h0f);
// write_register(8'd25, 8'hed);
// write_register(8'd26, 8'hcb);
// write_register(8'd27, 8'ha9);
// write_register(8'd28, 8'h87);
*/
// Extended frame format
// Writing TX frame information + identifier + data
write_register(8'd16, 8'hc5); // Frame format = 1, Remote transmision request = 1, DLC = 5
write_register(8'd17, 8'ha6); // ID[28:21] = a6
write_register(8'd18, 8'h00); // ID[20:13] = 00
write_register(8'd19, 8'h5a); // ID[12:5] = 5a
write_register(8'd20, 8'ha8); // ID[4:0] = 15
// write_register(8'd21, 8'h78); RTR does not send any data
// write_register(8'd22, 8'h9a);
// write_register(8'd23, 8'hbc);
// write_register(8'd24, 8'hde);
// write_register(8'd25, 8'hf0);
// write_register(8'd26, 8'h0f);
// write_register(8'd27, 8'hed);
// write_register(8'd28, 8'hcb);
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