Release 6.1i - netgen G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.Reading design can_top.ngd ...  Flattening design ...  Flattening design completed.  Specializing design ...Adding the appropriate PHYSONLY signals to the appropriate simprims.  Specializing design completed.  Preping physical only global signals ...  Preping design's networks ...  Preping design's macros ...Writing VHDL netlist can_top_translate.vhd ...Total memory usage is 41820 kilobytes