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-- You must compile the wrapper file multiplier.vhd when simulating
-- the core, multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY multiplier IS
	port (
	clk: IN std_logic;
	a: IN std_logic_VECTOR(11 downto 0);
	b: IN std_logic_VECTOR(11 downto 0);
	q: OUT std_logic_VECTOR(11 downto 0);
	aclr: IN std_logic);
END multiplier;

ARCHITECTURE multiplier_a OF multiplier IS

component wrapped_multiplier
	port (
	clk: IN std_logic;
	a: IN std_logic_VECTOR(11 downto 0);
	b: IN std_logic_VECTOR(11 downto 0);
	q: OUT std_logic_VECTOR(11 downto 0);
	aclr: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_multiplier use entity XilinxCoreLib.mult_gen_v6_0(behavioral)		generic map(
			c_a_type => 0,
			c_mem_type => 0,
			c_has_sclr => 0,
			c_has_q => 1,
			c_reg_a_b_inputs => 1,
			c_has_o => 0,
			bram_addr_width => 9,
			c_v2_speed => 1,
			c_baat => 12,
			c_output_hold => 0,
			c_b_constant => 0,
			c_has_loadb => 0,
			c_has_b => 1,
			c_use_luts => 0,
			c_has_rdy => 0,
			c_has_nd => 0,
			c_pipeline => 1,
			c_has_a_signed => 0,
			c_b_type => 0,
			c_sqm_type => 0,
			c_standalone => 1,
			c_b_value => "0000000000000001",
			c_enable_rlocs => 1,
			c_mult_type => 1,
			c_has_aclr => 1,
			c_mem_init_prefix => "mem",
			c_has_load_done => 0,
			c_has_swapb => 0,
			c_out_width => 12,
			c_b_width => 12,
			c_a_width => 12,
			c_has_rfd => 0,
			c_sync_enable => 1,
			c_has_ce => 0,
			c_stack_adders => 1);
BEGIN

U0 : wrapped_multiplier
		port map (
			clk => clk,
			a => a,
			b => b,
			q => q,
			aclr => aclr);
END multiplier_a;

-- synopsys translate_on