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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component costest
	port (
	THETA: IN std_logic_VECTOR(5 downto 0);
	CLK: IN std_logic;
	ACLR: IN std_logic;
	ND: IN std_logic;
	RFD: OUT std_logic;
	RDY: OUT std_logic;
	SINE: OUT std_logic_VECTOR(7 downto 0));
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of costest: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of costest: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : costest
		port map (
			THETA => THETA,
			CLK => CLK,
			ACLR => ACLR,
			ND => ND,
			RFD => RFD,
			RDY => RDY,
			SINE => SINE);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file costest.vhd when simulating
-- the core, costest. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".