--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2003 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file cosfunc_test.vhd when simulating
-- the core, cosfunc_test. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY cosfunc_test IS
	port (
	THETA: IN std_logic_VECTOR(6 downto 0);
	CLK: IN std_logic;
	ACLR: IN std_logic;
	COSINE: OUT std_logic_VECTOR(7 downto 0));
END cosfunc_test;

ARCHITECTURE cosfunc_test_a OF cosfunc_test IS

component wrapped_cosfunc_test
	port (
	THETA: IN std_logic_VECTOR(6 downto 0);
	CLK: IN std_logic;
	ACLR: IN std_logic;
	COSINE: OUT std_logic_VECTOR(7 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_cosfunc_test use entity XilinxCoreLib.C_SIN_COS_V4_2(behavioral)		generic map(
			c_has_clk => 1,
			c_reg_input => 1,
			c_has_rdy => 0,
			c_has_sclr => 0,
			c_symmetric => 1,
			c_reg_output => 1,
			c_has_nd => 0,
			c_enable_rlocs => 0,
			c_has_rfd => 0,
			c_negative_sine => 0,
			c_latency => 3,
			c_pipe_stages => 1,
			c_has_ce => 0,
			c_has_aclr => 1,
			c_outputs_required => 1,
			c_theta_width => 7,
			c_mem_type => 1,
			c_negative_cosine => 0,
			c_output_width => 8);
BEGIN

U0 : wrapped_cosfunc_test
		port map (
			THETA => THETA,
			CLK => CLK,
			ACLR => ACLR,
			COSINE => COSINE);
END cosfunc_test_a;

-- synopsys translate_on