# Xilinx CORE Generator 6.2.03i
SELECT Sine-Cosine_Look-Up_Table Virtex2 Xilinx,_Inc. 4.2
CSET output_width = 8
CSET handshaking_enabled = true
CSET negative_sine = false
CSET theta_input_width = 6
CSET output_options = Registered
CSET function = Sine_and_Cosine
CSET sclr_pin = false
CSET output_symmetry = Symmetric
CSET memory_type = Block_ROM
CSET clock_enable = false
CSET create_rpm = false
CSET negative_cosine = false
CSET pipeline_stages = 1
CSET input_options = Registered
CSET component_name = cosfunc
CSET aclr_pin = true
GENERATE