# Xilinx CORE Generator 6.2.03i
SELECT Multiplier Virtex2 Xilinx,_Inc. 6.0
CSET create_rpm = true
CSET clock_enable = false
CSET output_options = Registered
CSET port_b_constant = false
CSET port_a_input = Parallel
CSET reloadable = false
CSET port_b_width = 12
CSET nd = false
CSET multiplier_type = Parallel
CSET port_a_width = 12
CSET reload_options = Stop_During_Reload
CSET ce_overrides = CE_Overrides_SCLR
CSET memory_type = Distributed_Memory
CSET multiplier_construction = Use_Multiplier_Blocks_Virtex2
CSET port_a_data = Signed
CSET virtex2_multiplier_optimization = Speed
CSET rdy = false
CSET register_input = true
CSET port_b_data = Signed
CSET component_name = multiplier
CSET synchronous_clear = false
CSET asynchronous_clear = true
CSET load_done_output = false
CSET rfd = false
CSET clk_cycles_per_input = 1
CSET style = Rectangular_Shape
CSET port_b_constant_value = 1
CSET pipelined = Maximum
CSET output_hold_register = false
CSET output_width = 12
GENERATE