# Xilinx CORE Generator 6.2.03i
# Username = Chao.SEU
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = F:\FPGA_LMS3
# ExpandedProjectPath = F:\FPGA_LMS3
# OverwriteFiles = true
# Core name: costest
# Number of Primitives in design: 19
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 1
# Number of LUTs used in design: 1
# Number of REG used in design: 17
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 1
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Virtex2
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Sine-Cosine_Look-Up_Table Virtex2 Xilinx,_Inc. 4.2
CSET output_width = 8
CSET handshaking_enabled = true
CSET negative_sine = false
CSET theta_input_width = 6
CSET output_options = Registered
CSET function = Sine
CSET sclr_pin = false
CSET output_symmetry = Symmetric
CSET memory_type = Block_ROM
CSET clock_enable = false
CSET create_rpm = false
CSET negative_cosine = false
CSET pipeline_stages = 1
CSET input_options = Registered
CSET component_name = costest
CSET aclr_pin = true
GENERATE