?? lms.gfl
字號:
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# View RTL Schematic
lms.ngr
# ModelSim : Launch ModelSim Simulator
lms.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# VHDL : View VHDL Instantiation Template
__projnav/tb.rsp
lms.vhi
__projnav/vhd2vhi.err
# ModelSim : Launch ModelSim Simulator
lms.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
test_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_fortest_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) :
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -