Release 6.2i - xst G.31aCopyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.76 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.76 s | Elapsed : 0.00 / 1.00 s --> Reading design: costest.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : costest.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : costestOutput Format                      : NGCTarget Device                      : xc2v1000-4-fg256---- Source OptionsTop Module Name                    : costestAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 16Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : costest.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NOtristate2logic                     : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS3/costest.vhd. Ignore this file from project file costest_vhdl.prj.FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover.  Process will terminate.  To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com