[COREGEN.VERILOG Component Instantiation.cosfunc]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="cosfunc YourInstanceName ("
text007="    .THETA(THETA),"
text008="    .CLK(CLK),"
text009="    .ACLR(ACLR),"
text010="    .ND(ND),"
text011="    .RFD(RFD),"
text012="    .RDY(RDY),"
text013="    .SINE(SINE),"
text014="    .COSINE(COSINE));"
text015=""
text016=" "
type=template
[COREGEN.VERILOG Component Instantiation.cosfunc_test]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="cosfunc_test YourInstanceName ("
text007="    .THETA(THETA),"
text008="    .CLK(CLK),"
text009="    .ACLR(ACLR),"
text010="    .COSINE(COSINE));"
text011=""
text012=" "
type=template
[COREGEN.VERILOG Component Instantiation.costest]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="costest YourInstanceName ("
text007="    .THETA(THETA),"
text008="    .CLK(CLK),"
text009="    .ACLR(ACLR),"
text010="    .ND(ND),"
text011="    .RFD(RFD),"
text012="    .RDY(RDY),"
text013="    .SINE(SINE));"
text014=""
text015=" "
type=template
[COREGEN.VERILOG Component Instantiation.multiplier]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="multiplier YourInstanceName ("
text007="    .clk(clk),"
text008="    .a(a),"
text009="    .b(b),"
text010="    .q(q),"
text011="    .aclr(aclr));"
text012=""
text013=" "
type=template
[COREGEN.VHDL Component Instantiation.cosfunc]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component cosfunc"
text005="    port ("
text006="    THETA: IN std_logic_VECTOR(5 downto 0);"
text007="    CLK: IN std_logic;"
text008="    ACLR: IN std_logic;"
text009="    ND: IN std_logic;"
text010="    RFD: OUT std_logic;"
text011="    RDY: OUT std_logic;"
text012="    SINE: OUT std_logic_VECTOR(7 downto 0);"
text013="    COSINE: OUT std_logic_VECTOR(7 downto 0));"
text014="end component;"
text015=""
text016=""
text017=""
text018=" "
text019="-------------------------------------------------------------"
text020=" "
text021="-- The following code must appear in the VHDL architecture body."
text022="-- Substitute your own instance name and net names."
text023=" "
text024="your_instance_name : cosfunc"
text025="        port map ("
text026="            THETA => THETA,"
text027="            CLK => CLK,"
text028="            ACLR => ACLR,"
text029="            ND => ND,"
text030="            RFD => RFD,"
text031="            RDY => RDY,"
text032="            SINE => SINE,"
text033="            COSINE => COSINE);"
text034=" "
type=template
[COREGEN.VHDL Component Instantiation.cosfunc_test]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component cosfunc_test"
text005="    port ("
text006="    THETA: IN std_logic_VECTOR(6 downto 0);"
text007="    CLK: IN std_logic;"
text008="    ACLR: IN std_logic;"
text009="    COSINE: OUT std_logic_VECTOR(7 downto 0));"
text010="end component;"
text011=""
text012=""
text013=""
text014=" "
text015="-------------------------------------------------------------"
text016=" "
text017="-- The following code must appear in the VHDL architecture body."
text018="-- Substitute your own instance name and net names."
text019=" "
text020="your_instance_name : cosfunc_test"
text021="        port map ("
text022="            THETA => THETA,"
text023="            CLK => CLK,"
text024="            ACLR => ACLR,"
text025="            COSINE => COSINE);"
text026=" "
type=template
[COREGEN.VHDL Component Instantiation.costest]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component costest"
text005="    port ("
text006="    THETA: IN std_logic_VECTOR(5 downto 0);"
text007="    CLK: IN std_logic;"
text008="    ACLR: IN std_logic;"
text009="    ND: IN std_logic;"
text010="    RFD: OUT std_logic;"
text011="    RDY: OUT std_logic;"
text012="    SINE: OUT std_logic_VECTOR(7 downto 0));"
text013="end component;"
text014=""
text015=""
text016=""
text017=" "
text018="-------------------------------------------------------------"
text019=" "
text020="-- The following code must appear in the VHDL architecture body."
text021="-- Substitute your own instance name and net names."
text022=" "
text023="your_instance_name : costest"
text024="        port map ("
text025="            THETA => THETA,"
text026="            CLK => CLK,"
text027="            ACLR => ACLR,"
text028="            ND => ND,"
text029="            RFD => RFD,"
text030="            RDY => RDY,"
text031="            SINE => SINE);"
text032=" "
type=template
[COREGEN.VHDL Component Instantiation.multiplier]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component multiplier"
text005="    port ("
text006="    clk: IN std_logic;"
text007="    a: IN std_logic_VECTOR(11 downto 0);"
text008="    b: IN std_logic_VECTOR(11 downto 0);"
text009="    q: OUT std_logic_VECTOR(11 downto 0);"
text010="    aclr: IN std_logic);"
text011="end component;"
text012=""
text013=""
text014=""
text015=" "
text016="-------------------------------------------------------------"
text017=" "
text018="-- The following code must appear in the VHDL architecture body."
text019="-- Substitute your own instance name and net names."
text020=" "
text021="your_instance_name : multiplier"
text022="        port map ("
text023="            clk => clk,"
text024="            a => a,"
text025="            b => b,"
text026="            q => q,"
text027="            aclr => aclr);"
text028=" "
type=template