-- VHDL Test Bench Created from source file lms.vhd -- 22:08:05 07/05/2005
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY lms_ForTest_vhd_tb IS
END lms_ForTest_vhd_tb;

ARCHITECTURE behavior OF lms_ForTest_vhd_tb IS 

	COMPONENT lms
	PORT(
		waveIN : IN std_logic_vector(7 downto 0);
		start : IN std_logic;
		CLK : IN std_logic;          
		waveOut : OUT std_logic_vector(7 downto 0);
		eOut : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

  COMPONENT cosfunc_test    PORT (            THETA   : IN  std_logic_VECTOR(4 downto 0);            CLK     : IN  std_logic;            ACLR    : IN  std_logic;            COSINE  : OUT std_logic_VECTOR(7 downto 0)
          );    END COMPONENT;



	SIGNAL waveIN :  std_logic_vector(7 downto 0);
	SIGNAL waveOut :  std_logic_vector(7 downto 0);
	SIGNAL eOut :  std_logic_vector(7 downto 0);
	SIGNAL start :  std_logic;
	SIGNAL CLK :  std_logic;

signal THETA :	 std_logic_VECTOR(4 downto 0);
signal ACLR :	 std_logic;
signal COSINE :	 std_logic_VECTOR(7 downto 0);

signal wave:   std_logic_vector(7 downto 0);

BEGIN

	uut: lms PORT MAP(
		waveIN => wave,
		waveOut => waveOut,
		eOut => eOut,
		start => start,
		CLK => CLK
	);

     uut2: cosfunc_test             PORT MAP(                       THETA   => THETA,                       CLK     => CLK,                       ACLR    => ACLR,                       COSINE  => wave
				  );



------------------------------------------------------------------------------------------

Initial : PROCESS
   
	           BEGIN
	 
	              start <='0';
	              ACLR  <='1';  
				           WAIT FOR 15.0 ns;
			    start <='1';
			    ACLR  <='0';
				           WAIT;
   
	       END PROCESS;

------------------------------------------------------------------------------------------

sTHETA:PROCESS
		 
		   BEGIN	  	     		
		 
			   WAIT UNTIL ( clk'EVENT AND clk='1' );
							  
							  IF(start = '1') THEN			   -- "start" signal.

							     THETA <= THETA + 1;	                                       
							  
							  ELSE

								THETA  <= "00000";
							  
							  END IF;               

		   END PROCESS;	


------------------------------------------------------------------------------------------

ClkGenerate: PROCESS
	         
			   BEGIN
		
		              WAIT FOR 13 ns;                -- Clock: 100MHz 
		                  
					   IF CLK  = '1' then			               
						 CLK <= '0';		        
			             ELSE
			                CLK <= '1';
		                  END IF;
	      
		    END PROCESS;



END;