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--                                TestBench of LMS Module.
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LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.ALL;
USE     IEEE.STD_LOGIC_ARITH.ALL;
USE     IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY LMS_test_tb IS
END    LMS_test_tb;

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ARCHITECTURE behavior OF LMS_test_tb IS 

COMPONENT LMS
    PORT (          
           waveIN    : OUT std_logic_vector(7 DOWNTO 0);
           waveOut   : OUT std_logic_vector(7 DOWNTO 0);       
           eOut      : OUT std_logic_vector(7 DOWNTO 0);

           start     : IN  std_logic; 		                          
           CLK       : IN  std_logic
	    );   
END COMPONENT;

	SIGNAL CLK      :  std_logic;
	SIGNAL start    :  std_logic;

	SIGNAL waveIN   :  std_logic_vector(7 downto 0);
	SIGNAL waveOut  :  std_logic_vector(7 downto 0);
	SIGNAL eOut     :  std_logic_vector(7 downto 0);



BEGIN

	U1: LMS  
	       PORT MAP(
		            waveIN  =>  waveIN,
                      waveOut =>  waveOut,       
                      eOut    =>  eOut,      
                     
				  start   =>  start, 		                          
                      CLK     =>  CLK
	               );

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Initial : PROCESS
   
	          BEGIN
	 
	              start <='0';
				           WAIT FOR 6.0 ns;
			    start <='1';
				        
   						 WAIT;
	      END PROCESS;

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GenerateCLK: PROCESS
	         
			   BEGIN
		
		              WAIT FOR 6.0 ns;                -- half period = 6.0 ns 
		                  
					   IF( CLK  = '1' ) then			               

						       CLK <= '0';		        
			             ELSE

			                      CLK <= '1';
		                  END IF;
	      
		   END PROCESS;

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END behavior;