LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY add IS
  PORT(a:in STD_LOGIC_VECTOR(3 DOWNTO 0);
       b:in STD_LOGIC_VECTOR(3 DOWNTO 0);
       cin:in STD_LOGIC;
       sum:out STD_LOGIC_VECTOR(3 DOWNTO 0);
       count:out STD_LOGIC
);
END add;
ARCHITECTURE add_arch OF add IS
SIGNAL C:STD_LOGIC_VECTOR(4 DOWNTO 0);
begin
    process(a,b,cin,c)
begin
  --<<enter your statements here>>
  c(0)<=cin;
  for i in 0 to 3 loop
       sum(i)<=a(i) xor b(i) xor c(i);
       c(i+1)<=(a(i) and b(i)) or (c(i) and (a(i) or b(i)));
  end loop;
count<=c(4);
end process;
end add_arch;