;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment.
;
; $Revision: 1.56 $
;
;-----------------------------------------------------------------------------
	
;
; Naming covention of labels in this file:
;
;  ?xxx	  - External labels only accessed from assembler.
;  __xxx  - External labels accessed from or defined in C.
;  xxx	  - Labels local to one module (note: this file contains
;           several modules).
;  main	  - The starting point of the user program.
;

;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode
	

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------

        MODULE	?RESET
        COMMON	INTVEC:CODE:NOROOT(2)
        PUBLIC  __program_start
        EXTERN	?cstartup
        IMPORT  OS_CPU_ARM_ExceptUndefInstrHndlr
        IMPORT  OS_CPU_ARM_ExceptSwiHndlr
        IMPORT  OS_CPU_ARM_ExceptPrefetchAbortHndlr
        IMPORT  OS_CPU_ARM_ExceptDataAbortHndlr
        IMPORT  OS_CPU_ARM_ExceptIrqHndlr
        IMPORT  OS_CPU_ARM_ExceptFiqHndlr
		CODE32	                ; Always ARM mode after reset	

        org	0x00
__program_start:
		ldr	    pc, [pc,#24]    ; Absolute jump can reach 4 GByte
;		ldr	    b,  ?cstartup   ; Relative branch allows remap, limited to 32 MByte
                                ; Vectors can be enabled by removing the comments below or by
                                ; using #pragma vector from C code.
        org	    0x04
        ldr     pc, [pc,#24]    ; Branch to undef_handler

        org	    0x08
        ldr     pc, [pc,#24]    ; Branch to swi_handler

        org	    0x0c
        ldr     pc, [pc,#24]    ; Branch to prefetch_handler

        org	    0x10
        ldr     pc, [pc,#24]    ; Branch to data_handler

		org	    0x18
		ldr	    pc, [pc,#24]	; Branch to irq_handler

		org	    0x1c
		ldr	    pc, [pc,#24]	; Branch to fiq_handler

		                        ; Constant table entries (for ldr pc) will be placed at 0x20
                                ; Exception vectors can be specified in C code by #pragma vector or by filling
                                ; in the vectors below. The vector address is the ARM vector number + 0x20.
		org	    0x20
        dc32    ?cstartup
		org	    0x24
        dc32    OS_CPU_ARM_ExceptUndefInstrHndlr
		org	    0x28
        dc32    OS_CPU_ARM_ExceptSwiHndlr
		org	    0x2c
        dc32    OS_CPU_ARM_ExceptPrefetchAbortHndlr
		org	    0x30
        dc32    OS_CPU_ARM_ExceptDataAbortHndlr
		org	    0x38
        dc32    OS_CPU_ARM_ExceptIrqHndlr
		org	    0x3c
        dc32    OS_CPU_ARM_ExceptFiqHndlr

        ENDMOD


;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
		MODULE	?CSTARTUP

		RSEG	IRQ_STACK:DATA(2)
		
		RSEG	ABT_STACK:DATA:NOROOT(2)
		RSEG	UND_STACK:DATA:NOROOT(2)
		RSEG	FIR_STACK:DATA:NOROOT(2)
		RSEG	SVC_STACK:DATA:NOROOT(2)
		RSEG	CSTACK:DATA(2)
		RSEG	ICODE:CODE:NOROOT(2)

		PUBLIC	?cstartup
		EXTERN	?main

; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.

		CODE32
?cstartup

; Add initialization nedded before setup of stackpointers here


; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.

                mrs     r0,cpsr                             ; Original PSR value
                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8     ; End of IRQ_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#ABT_MODE                     ; Set Abort mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(ABT_STACK) & 0xFFFFFFF8     ; End of ABT_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#SVC_MODE                     ; Set Supervisor mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(SVC_STACK) & 0xFFFFFFF8     ; End of SVC_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#UND_MODE                     ; Set Undefined mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(UND_STACK) & 0xFFFFFFF8     ; End of FIR_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#FIQ_MODE                     ; Set FIR mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(FIR_STACK) & 0xFFFFFFF8     ; End of FIR_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(CSTACK) & 0xFFFFFFF8        ; End of CSTACK


#ifdef __ARMVFP__
; Enable the VFP coprocessor.
                mov     r0, #0x40000000                 ; Set EN bit in VFP
                fmxr    fpexc, r0                       ; FPEXC, clear others.

; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
                mov     r0, #0x01000000		        ; Set FZ bit in VFP
                fmxr    fpscr, r0                       ; FPSCR, clear others.
#endif

; Add more initialization here


; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main
                bx      r0

                LTORG

                ENDMOD

                END