?? iolpc2104.h
字號:
} __pllfeed_bits;
/* Power control register */
typedef struct {
__REG32 IDL :1;
__REG32 PD :1;
__REG32 :30;
} __pcon_bits;
/* Power control for peripherals register */
typedef struct {
__REG32 :1;
__REG32 PCTIM0 :1;
__REG32 PCTIM1 :1;
__REG32 PCURT0 :1;
__REG32 PCURT1 :1;
__REG32 PCPWM0 :1;
__REG32 :1;
__REG32 PCI2C :1;
__REG32 PCSPI :1;
__REG32 PCRTC :1;
__REG32 :22;
} __pconp_bits;
/* VPB divider register */
typedef struct {
__REG32 VPBDIV :2;
__REG32 :30;
} __vpbdiv_bits;
#endif /* __IAR_SYSTEMS_ICC__ */
/* Common declarations ****************************************************/
/***************************************************************************
**
** VIC
**
***************************************************************************/
__IO_REG32_BIT(VICIRQStatus, 0xFFFFF000,__READ,__vicint_bits);
__IO_REG32_BIT(VICFIQStatus, 0xFFFFF004,__READ,__vicint_bits);
__IO_REG32_BIT(VICRawIntr, 0xFFFFF008,__READ,__vicint_bits);
__IO_REG32_BIT(VICIntSelect, 0xFFFFF00C,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnable, 0xFFFFF010,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnClear, 0xFFFFF014,__WRITE,__vicint_bits);
__IO_REG32_BIT(VICSoftInt, 0xFFFFF018,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICSoftIntClear, 0xFFFFF01C,__WRITE,__vicint_bits);
__IO_REG32_BIT(VICProtection, 0xFFFFF020,__READ_WRITE,__vicprotection_bits);
__IO_REG32(VICVectAddr, 0xFFFFF030,__READ_WRITE);
__IO_REG32(VICDefVectAddr, 0xFFFFF034,__READ_WRITE);
__IO_REG32(VICVectAddr0, 0xFFFFF100,__READ_WRITE);
__IO_REG32(VICVectAddr1, 0xFFFFF104,__READ_WRITE);
__IO_REG32(VICVectAddr2, 0xFFFFF108,__READ_WRITE);
__IO_REG32(VICVectAddr3, 0xFFFFF10C,__READ_WRITE);
__IO_REG32(VICVectAddr4, 0xFFFFF110,__READ_WRITE);
__IO_REG32(VICVectAddr5, 0xFFFFF114,__READ_WRITE);
__IO_REG32(VICVectAddr6, 0xFFFFF118,__READ_WRITE);
__IO_REG32(VICVectAddr7, 0xFFFFF11C,__READ_WRITE);
__IO_REG32(VICVectAddr8, 0xFFFFF120,__READ_WRITE);
__IO_REG32(VICVectAddr9, 0xFFFFF124,__READ_WRITE);
__IO_REG32(VICVectAddr10, 0xFFFFF128,__READ_WRITE);
__IO_REG32(VICVectAddr11, 0xFFFFF12C,__READ_WRITE);
__IO_REG32(VICVectAddr12, 0xFFFFF130,__READ_WRITE);
__IO_REG32(VICVectAddr13, 0xFFFFF134,__READ_WRITE);
__IO_REG32(VICVectAddr14, 0xFFFFF138,__READ_WRITE);
__IO_REG32(VICVectAddr15, 0xFFFFF13C,__READ_WRITE);
__IO_REG32_BIT(VICVectCntl0, 0xFFFFF200,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl1, 0xFFFFF204,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl2, 0xFFFFF208,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl3, 0xFFFFF20C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl4, 0xFFFFF210,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl5, 0xFFFFF214,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl6, 0xFFFFF218,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl7, 0xFFFFF21C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl8, 0xFFFFF220,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl9, 0xFFFFF224,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl10, 0xFFFFF228,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl11, 0xFFFFF22C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl12, 0xFFFFF230,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl13, 0xFFFFF234,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl14, 0xFFFFF238,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl15, 0xFFFFF23C,__READ_WRITE,__vicvectcntl_bits);
/***************************************************************************
**
** Pin connect block
**
***************************************************************************/
__IO_REG32_BIT(PINSEL0, 0xE002C000,__READ_WRITE,__pinsel0_bits);
__IO_REG32_BIT(PINSEL1, 0xE002C004,__READ_WRITE,__pinsel1_bits);
/***************************************************************************
**
** GPIO
**
***************************************************************************/
__IO_REG32_BIT(IOPIN, 0xE0028000,__READ,__gpio_bits);
__IO_REG32_BIT(IOSET, 0xE0028004,__READ_WRITE,__gpio_bits);
__IO_REG32_BIT(IODIR, 0xE0028008,__READ_WRITE,__gpio_bits);
__IO_REG32_BIT(IOCLR, 0xE002800C,__WRITE,__gpio_bits);
/***************************************************************************
**
** UART0
**
***************************************************************************/
/* U0DLL, U0RBR and U0THR share the same address */
__IO_REG8(U0RBRTHR, 0xE000C000,__READ_WRITE);
#define U0DLL U0RBRTHR
#define U0RBR U0RBRTHR
#define U0THR U0RBRTHR
/* U0DLM and U0IER share the same address */
__IO_REG8_BIT(U0IER, 0xE000C004,__READ_WRITE,__uartier0_bits);
#define U0DLM U0IER
/* U0FCR and U0IIR share the same address */
__IO_REG8_BIT(U0FCR, 0xE000C008,__READ_WRITE,__uartfcriir_bits);
#define U0IIR_bit U0FCR_bit
#define U0IIR U0FCR
__IO_REG8_BIT(U0LCR, 0xE000C00C,__READ_WRITE,__uartlcr_bits);
__IO_REG8_BIT(U0LSR, 0xE000C014,__READ_WRITE,__uartlsr_bits);
__IO_REG8(U0SCR, 0xE000C01C,__READ_WRITE);
/***************************************************************************
**
** UART1
**
***************************************************************************/
/* U1DLL, U1RBR and U1THR share the same address */
__IO_REG8(U1RBRTHR, 0xE0010000,__READ_WRITE);
#define U1DLL U1RBRTHR
#define U1RBR U1RBRTHR
#define U1THR U1RBRTHR
/* U1DLM and U1IER share the same address */
__IO_REG8_BIT(U1IER, 0xE0010004,__READ_WRITE,__uartier1_bits);
#define U1DLM U1IER
/* U1FCR and U1IIR share the same address */
__IO_REG8_BIT(U1FCR, 0xE0010008,__READ_WRITE,__uartfcriir_bits);
#define U1IIR_bit U1FCR_bit
#define U1IIR U1FCR
__IO_REG8_BIT(U1MCR, 0xE0010010,__READ_WRITE,__uartmcr_bits);
__IO_REG8_BIT(U1LCR, 0xE001000C,__READ_WRITE,__uartlcr_bits);
__IO_REG8_BIT(U1LSR, 0xE0010014,__READ_WRITE,__uartlsr_bits);
__IO_REG8_BIT(U1MSR, 0xE0010018,__READ_WRITE,__uartmsr_bits);
__IO_REG8(U1SCR, 0xE001001C,__READ_WRITE);
/***************************************************************************
**
** I2C
**
***************************************************************************/
__IO_REG32_BIT(I2CONSET, 0xE001C000,__READ_WRITE,__i2conset_bits);
__IO_REG32_BIT(I2STAT, 0xE001C004,__READ,__i2stat_bits);
__IO_REG32_BIT(I2DAT, 0xE001C008,__READ_WRITE,__i2dat_bits);
__IO_REG32_BIT(I2ADR, 0xE001C00C,__READ_WRITE,__i2adr_bits);
__IO_REG32_BIT(I2SCLH, 0xE001C010,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2SCLL, 0xE001C014,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2CONCLR, 0xE001C018,__WRITE,__i2conclr_bits);
/***************************************************************************
**
** SPI
**
***************************************************************************/
__IO_REG32_BIT(S0SPCR, 0xE0020000,__READ_WRITE,__spcr_bits);
__IO_REG32_BIT(S0SPSR, 0xE0020004,__READ,__spsr_bits);
__IO_REG32_BIT(S0SPDR, 0xE0020008,__READ_WRITE,__spdr_bits);
__IO_REG32_BIT(S0SPCCR, 0xE002000C,__READ_WRITE,__spccr_bits);
__IO_REG32_BIT(S0SPINT, 0xE002001C,__READ_WRITE,__spint_bits);
/***************************************************************************
**
** TIMER0
**
***************************************************************************/
__IO_REG32_BIT(T0IR, 0xE0004000,__READ_WRITE,__ir_bits);
__IO_REG32_BIT(T0TCR, 0xE0004004,__READ_WRITE,__tcr_bits);
__IO_REG32(T0TC, 0xE0004008,__READ_WRITE);
__IO_REG32(T0PR, 0xE000400c,__READ_WRITE);
__IO_REG32(T0PC, 0xE0004010,__READ_WRITE);
__IO_REG32_BIT(T0MCR, 0xE0004014,__READ_WRITE,__mcr_bits);
__IO_REG32(T0MR0, 0xE0004018,__READ_WRITE);
__IO_REG32(T0MR1, 0xE000401C,__READ_WRITE);
__IO_REG32(T0MR2, 0xE0004020,__READ_WRITE);
__IO_REG32(T0MR3, 0xE0004024,__READ_WRITE);
__IO_REG32_BIT(T0CCR, 0xE0004028,__READ_WRITE,__ccr0_bits);
__IO_REG32(T0CR0, 0xE000402C,__READ);
__IO_REG32(T0CR1, 0xE0004030,__READ);
__IO_REG32(T0CR2, 0xE0004034,__READ);
__IO_REG32(T0CR3, 0xE0004038,__READ);
__IO_REG32_BIT(T0EMR, 0xE000403c,__READ_WRITE,__emr_bits);
/***************************************************************************
**
** TIMER1
**
***************************************************************************/
__IO_REG32_BIT(T1IR, 0xE0008000,__READ_WRITE,__ir_bits);
__IO_REG32_BIT(T1TCR, 0xE0008004,__READ_WRITE,__tcr_bits);
__IO_REG32(T1TC, 0xE0008008,__READ_WRITE);
__IO_REG32(T1PR, 0xE000800c,__READ_WRITE);
__IO_REG32(T1PC, 0xE0008010,__READ_WRITE);
__IO_REG32_BIT(T1MCR, 0xE0008014,__READ_WRITE,__mcr_bits);
__IO_REG32(T1MR0, 0xE0008018,__READ_WRITE);
__IO_REG32(T1MR1, 0xE000801C,__READ_WRITE);
__IO_REG32(T1MR2, 0xE0008020,__READ_WRITE);
__IO_REG32(T1MR3, 0xE0008024,__READ_WRITE);
__IO_REG32_BIT(T1CCR, 0xE0008028,__READ_WRITE,__ccr1_bits);
__IO_REG32(T1CR0, 0xE000802C,__READ);
__IO_REG32(T1CR1, 0xE0008030,__READ);
__IO_REG32(T1CR2, 0xE0008034,__READ);
__IO_REG32(T1CR3, 0xE0008038,__READ);
__IO_REG32_BIT(T1EMR, 0xE000803c,__READ_WRITE,__emr_bits);
/***************************************************************************
**
** PWM
**
***************************************************************************/
__IO_REG32_BIT(PWMIR, 0xE0014000,__READ_WRITE,__pwmir_bits);
__IO_REG32_BIT(PWMTCR, 0xE0014004,__READ_WRITE,__pwmtcr_bits);
__IO_REG32(PWMTC, 0xE0014008,__READ_WRITE);
__IO_REG32(PWMPR, 0xE001400C,__READ_WRITE);
__IO_REG32(PWMPC, 0xE0014010,__READ_WRITE);
__IO_REG32_BIT(PWMMCR, 0xE0014014,__READ_WRITE,__pwmmcr_bits);
__IO_REG32(PWMMR0, 0xE0014018,__READ_WRITE);
__IO_REG32(PWMMR1, 0xE001401C,__READ_WRITE);
__IO_REG32(PWMMR2, 0xE0014020,__READ_WRITE);
__IO_REG32(PWMMR3, 0xE0014024,__READ_WRITE);
__IO_REG32(PWMMR4, 0xE0014040,__READ_WRITE);
__IO_REG32(PWMMR5, 0xE0014044,__READ_WRITE);
__IO_REG32(PWMMR6, 0xE0014048,__READ_WRITE);
__IO_REG32_BIT(PWMPCR, 0xE001404C,__READ_WRITE,__pwmpcr_bits);
__IO_REG32_BIT(PWMLER, 0xE0014050,__READ_WRITE,__pwmler_bits);
/***************************************************************************
**
** RTC
**
***************************************************************************/
__IO_REG32_BIT(ILR, 0xE0024000,__READ_WRITE,__ilr_bits);
__IO_REG32_BIT(CTC, 0xE0024004,__READ,__ctc_bits);
__IO_REG32_BIT(CCR, 0xE0024008,__READ_WRITE,__rtcccr_bits);
__IO_REG32_BIT(CIIR, 0xE002400C,__READ_WRITE,__ciir_bits);
__IO_REG32_BIT(AMR, 0xE0024010,__READ_WRITE,__amr_bits);
__IO_REG32_BIT(CTIME0, 0xE0024014,__READ,__ctime0_bits);
__IO_REG32_BIT(CTIME1, 0xE0024018,__READ,__ctime1_bits);
__IO_REG32_BIT(CTIME2, 0xE002401C,__READ,__ctime2_bits);
__IO_REG32_BIT(SEC, 0xE0024020,__READ_WRITE,__sec_bits);
__IO_REG32_BIT(MIN, 0xE0024024,__READ_WRITE,__min_bits);
__IO_REG32_BIT(HOUR, 0xE0024028,__READ_WRITE,__hour_bits);
__IO_REG32_BIT(DOM, 0xE002402C,__READ_WRITE,__dom_bits);
__IO_REG32_BIT(DOW, 0xE0024030,__READ_WRITE,__dow_bits);
__IO_REG32_BIT(DOY, 0xE0024034,__READ_WRITE,__doy_bits);
__IO_REG32_BIT(MONTH, 0xE0024038,__READ_WRITE,__month_bits);
__IO_REG32_BIT(YEAR, 0xE002403C,__READ_WRITE,__year_bits);
__IO_REG32_BIT(ALSEC, 0xE0024060,__READ_WRITE,__sec_bits);
__IO_REG32_BIT(ALMIN, 0xE0024064,__READ_WRITE,__min_bits);
__IO_REG32_BIT(ALHOUR, 0xE0024068,__READ_WRITE,__hour_bits);
__IO_REG32_BIT(ALDOM, 0xE002406C,__READ_WRITE,__dom_bits);
__IO_REG32_BIT(ALDOW, 0xE0024070,__READ_WRITE,__dow_bits);
__IO_REG32_BIT(ALDOY, 0xE0024074,__READ_WRITE,__doy_bits);
__IO_REG32_BIT(ALMON, 0xE0024078,__READ_WRITE,__month_bits);
__IO_REG32_BIT(ALYEAR, 0xE002407C,__READ_WRITE,__year_bits);
__IO_REG32_BIT(PREINT, 0xE0024080,__READ_WRITE,__preint_bits);
__IO_REG32_BIT(PREFRAC, 0xE0024084,__READ_WRITE,__prefrac_bits);
/***************************************************************************
**
** Watchdog
**
***************************************************************************/
__IO_REG32_BIT(WDMOD, 0xE0000000,__READ_WRITE,__wdmod_bits);
__IO_REG32(WDTC, 0xE0000004,__READ_WRITE);
__IO_REG32_BIT(WDFEED, 0xE0000008,__WRITE,__wdfeed_bits);
__IO_REG32(WDTV, 0xE000000C,__READ);
/***************************************************************************
**
** System control block
**
***************************************************************************/
__IO_REG32_BIT(MAMCR, 0xE01FC000,__READ_WRITE,__mamcr_bits);
__IO_REG32_BIT(MAMTIM, 0xE01FC004,__READ_WRITE,__mamtim_bits);
__IO_REG32_BIT(EXTINT, 0xE01FC140,__READ_WRITE,__extint_bits);
__IO_REG32_BIT(EXTWAKE, 0xE01FC144,__READ_WRITE,__extwake_bits);
__IO_REG32_BIT(MEMMAP, 0xE01FC040,__READ_WRITE,__memmap_bits);
__IO_REG32_BIT(PLLCON, 0xE01FC080,__READ_WRITE,__pllcon_bits);
__IO_REG32_BIT(PLLCFG, 0xE01FC084,__READ_WRITE,__pllcfg_bits);
__IO_REG32_BIT(PLLSTAT, 0xE01FC088,__READ,__pllstat_bits);
__IO_REG32_BIT(PLLFEED, 0xE01FC08C,__READ_WRITE,__pllfeed_bits);
__IO_REG32_BIT(PCON, 0xE01FC0C0,__READ_WRITE,__pcon_bits);
__IO_REG32_BIT(PCONP, 0xE01FC0C4,__READ_WRITE,__pconp_bits);
__IO_REG32_BIT(VPBDIV, 0xE01FC100,__READ_WRITE,__vpbdiv_bits);
/***************************************************************************
** Assembler specific declarations
***************************************************************************/
#ifdef __IAR_SYSTEMS_ASM__
#endif /* __IAR_SYSTEMS_ASM__ */
/***************************************************************************
**
** Interrupt vector table
**
***************************************************************************/
#define RESETV 0x00 /* Reset */
#define UNDEFV 0x04 /* Undefined instruction */
#define SWIV 0x08 /* Software interrupt */
#define PABORTV 0x0c /* Prefetch abort */
#define DABORTV 0x10 /* Data abort */
#define IRQV 0x18 /* Normal interrupt */
#define FIQV 0x1c /* Fast interrupt */
/***************************************************************************
**
** VIC Interrupt channels
**
***************************************************************************/
#define VIC_WDT 0 /* Watchdog */
#define VIC_SW 1 /* Software interrupts */
#define VIC_DEBUGRX 2 /* Embedded ICE, DbgCommRx */
#define VIC_DEBUGTX 3 /* Embedded ICE, DbgCommTx */
#define VIC_TIMER0 4 /* Timer 0 (Match 0-3 Capture 0-3) */
#define VIC_TIMER1 5 /* Timer 1 (Match 0-3 Capture 0-3) */
#define VIC_UART0 6 /* UART 0 (RLS, THRE, RDA, CTI) */
#define VIC_UART1 7 /* UART 1 (RLS, THRE, RDA, CTI, MSI) */
#define VIC_PWM0 8 /* PWM 0 (Match 0-6 Capture 0-3) */
#define VIC_I2C 9 /* I2C (SI) */
#define VIC_SPI 10 /* SPI (SPIF, MODF) */
//#define VIC_RES 11 /* Reserved */
#define VIC_PLL 12 /* PLL lock (PLOCK) */
#define VIC_RTC 13 /* RTC (RTCCIF, RTCALF) */
#define VIC_EINT0 14 /* External interrupt 0 (EINT0) */
#define VIC_EINT1 15 /* External interrupt 1 (EINT1) */
#define VIC_EINT2 16 /* External interrupt 2 (EINT2) */
#endif /* __IOLPC2104_H */
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