?? bchanle.rpt
字號:
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 bchclk
126 - - - -- INPUT ^ 0 0 0 1 clr_b
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\lisha\bchanle.rpt
bchanle
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
110 - - - 02 OUTPUT 0 1 0 0 badress0
73 - - - 01 OUTPUT 0 1 0 0 badress1
8 - - A -- OUTPUT 0 1 0 0 badress2
7 - - A -- OUTPUT 0 1 0 0 badress3
100 - - A -- OUTPUT 0 1 0 0 badress4
101 - - A -- OUTPUT 0 1 0 0 badress5
109 - - - 01 OUTPUT 0 1 0 0 badress6
111 - - - 03 OUTPUT 0 1 0 0 badress7
112 - - - 04 OUTPUT 0 1 0 0 badress8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\lisha\bchanle.rpt
bchanle
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 01 AND2 0 4 0 4 |LPM_ADD_SUB:160|addcore:adder|:83
- 8 - A 02 AND2 0 2 0 1 |LPM_ADD_SUB:160|addcore:adder|:87
- 7 - A 02 AND2 0 4 0 2 |LPM_ADD_SUB:160|addcore:adder|:95
- 3 - A 03 DFFE + 0 1 1 0 :3
- 2 - A 03 DFFE + 0 1 1 0 :5
- 3 - A 02 DFFE + 0 1 1 0 :7
- 5 - A 02 DFFE + 0 1 1 0 :9
- 8 - A 05 DFFE + 0 1 1 0 :11
- 5 - A 04 DFFE + 0 1 1 0 :13
- 7 - A 01 DFFE + 0 1 1 0 :15
- 3 - A 01 DFFE + 0 1 1 0 :17
- 4 - A 01 DFFE + 0 1 1 0 :19
- 5 - A 03 DFFE + 0 3 0 2 acc8 (:21)
- 4 - A 03 DFFE + 0 2 0 3 acc7 (:22)
- 6 - A 02 DFFE + 0 3 0 3 acc6 (:23)
- 4 - A 02 DFFE + 0 3 0 4 acc5 (:24)
- 2 - A 04 DFFE + 0 2 0 5 acc4 (:25)
- 1 - A 04 DFFE + 0 2 0 3 acc3 (:26)
- 8 - A 01 DFFE + 0 3 0 3 acc2 (:27)
- 6 - A 01 DFFE + 0 2 0 4 acc1 (:28)
- 5 - A 01 DFFE + 0 1 0 5 acc0 (:29)
- 1 - A 02 OR2 0 3 0 1 :81
- 2 - A 02 AND2 0 3 0 1 :88
- 1 - A 01 OR2 0 3 0 2 :101
- 1 - A 03 OR2 ! 1 3 0 9 :114
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\lisha\bchanle.rpt
bchanle
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 9/ 72( 12%) 0/ 72( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\lisha\bchanle.rpt
bchanle
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 bchclk
Device-Specific Information: f:\lisha\bchanle.rpt
bchanle
** EQUATIONS **
bchclk : INPUT;
clr_b : INPUT;
-- Node name is ':29' = 'acc0'
-- Equation name is 'acc0', location is LC5_A1, type is buried.
acc0 = DFFE( _EQ001, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ001 = !acc0 & !_LC1_A3;
-- Node name is ':28' = 'acc1'
-- Equation name is 'acc1', location is LC6_A1, type is buried.
acc1 = DFFE( _EQ002, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ002 = !acc0 & acc1 & !_LC1_A3
# acc0 & !acc1 & !_LC1_A3;
-- Node name is ':27' = 'acc2'
-- Equation name is 'acc2', location is LC8_A1, type is buried.
acc2 = DFFE( _EQ003, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ003 = !acc1 & acc2 & !_LC1_A3
# !acc0 & acc2 & !_LC1_A3
# acc0 & acc1 & !acc2 & !_LC1_A3;
-- Node name is ':26' = 'acc3'
-- Equation name is 'acc3', location is LC1_A4, type is buried.
acc3 = DFFE( _EQ004, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ004 = acc3 & _LC1_A1 & !_LC1_A3
# !acc3 & !_LC1_A1 & !_LC1_A3;
-- Node name is ':25' = 'acc4'
-- Equation name is 'acc4', location is LC2_A4, type is buried.
acc4 = DFFE( _EQ005, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ005 = acc4 & !_LC1_A3 & !_LC2_A1
# !acc4 & !_LC1_A3 & _LC2_A1;
-- Node name is ':24' = 'acc5'
-- Equation name is 'acc5', location is LC4_A2, type is buried.
acc5 = DFFE( _EQ006, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ006 = !acc4 & acc5 & !_LC1_A3
# acc5 & !_LC1_A3 & !_LC2_A1
# acc4 & !acc5 & !_LC1_A3 & _LC2_A1;
-- Node name is ':23' = 'acc6'
-- Equation name is 'acc6', location is LC6_A2, type is buried.
acc6 = DFFE( _EQ007, GLOBAL( bchclk), VCC, VCC, VCC);
_EQ007 = acc6 & !_LC1_A3 & !_LC8_A2
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