JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 1091328509
SOURCE i2c_master_defines.v
SOURCE timescale.v
SOURCE i2c_master_byte_ctrl.v
SOURCE i2c_master_bit_ctrl.v
SOURCE i2c_master_top.v
STIMULUS i2c_slave_model.v
STIMULUS wb_master_model.v
STIMULUS tst_bench_top.v
[STATUS-ALL]
i2c_master_bit_ctrl.ngcFile=WARNINGS,1091328852
i2c_master_byte_ctrl.ngcFile=WARNINGS,1094996338
i2c_master_byte_ctrl.stxFile=WARNINGS,1094996295
i2c_master_top.ngcFile=WARNINGS,1094997273
i2c_master_top.stxFile=WARNINGS,1091328771
[STRATEGY-LIST]
Normal=True