/******************************************************************************\
* Copyright (C) 2004 by RTD Embedded Technologies, Inc.   All rights reserved.
* Confidential and Proprietary, Not for Public Release
*------------------------------------------------------------------------------
* PROJECT.......... Board Support Library for SPM6420 and SPM6430
* VERSION.......... (Defined in README.TXT)
*------------------------------------------------------------------------------
* CONTENT.......... Main source file of Board Support Library for SPM6420/6430
* FILENAME......... bsl_bsl.c
\******************************************************************************/
#define _BSL_BSL_MOD_

#include <bsl.h>

#include <std.h>
#include <csl.h>
#include <csl_emifa.h>
#include <csl_emifb.h>
#include <csl_pci.h>
#include <csl_irq.h>
#include <c6x.h>        // for SAVE_AMR, RESTORE_AMR, SAVE_SAT, RESTORE_SAT

#include <bsl_umisc.h>
#include <bsl_uint.h>


/******************************************************************************\
*                         L O C A L   S E C T I O N
\******************************************************************************/


/******************************************************************************\
* static macro declarations
\******************************************************************************/

// offsets of HW info variables in EEPROM
#define EEVAR_DSPNOMSP_OFFS         14  // DSP processor's nominal speed in MHz
#define EEVAR_FLASHSZ_OFFS          15  // size of the installed Flash memory in MB
#define EEVAR_SDRAMSZ_OFFS          16  // size of the installed SDRAM memory in MB

// EMIF Configuration for SPM6420/6430 board with 600 MHz DSP processor
// These are default configuration values, and are overridden in SPM6400_EMIF_INIT().
#define CFG_EMIFA_GBLCTL_600            0x00082024
#define CFG_EMIFA_CECTL0_600            0xFFFFFFDF
#define CFG_EMIFA_SDCTL_600             0x63116000
#define CFG_EMIFA_SDTIM_600             0x0000030C
#define CFG_EMIFA_SDEXT_600             0x00055C28
#define CFG_EMIFB_GBLCTL_600            0x00092024
#define CFG_EMIFB_CECTL0_600            0x13410D10
#define CFG_EMIFB_CECTL1_600            0x33514D10
#define CFG_EMIFB_CECTL2_600            0x33514D10
#define CFG_EMIFB_CECTL3_600            0x11814610


// function to configure the EMIF_A and EMIF_B according to the given SDRAM size
SPM6400_EMIF_INIT(int SDRAMSize)
{
    Uint32 PBus_temp, EMIFA_temp, EMIFB_temp;
    Uint32 Timer_Tick_Count;
    Uint16 pbctl_temp;
    TIMER_Handle hTimer;

    /*
        Setup SDRAM timing in EMIFA
    */

    EMIFA_temp = EMIFA_RGET(GBLCTL);
    EMIFA_temp &= 0xFFF0D007;
    EMIFA_temp |= 0x000820A0;
    EMIFA_RSET(GBLCTL, EMIFA_temp);

    // CECTL0
    EMIFA_RSET( CECTL0, 0xFFFFFFDF); // No reserved bits, just write a value

    // SDTIM
    EMIFA_temp = EMIFA_RGET(SDTIM);
    EMIFA_temp &= 0xFC000000;
    EMIFA_temp |= 0x00000190;
    EMIFA_RSET(SDTIM, EMIFA_temp);

    // SDEXT
    EMIFA_temp = EMIFA_RGET(SDEXT);
    EMIFA_temp &= 0xFFE00000;
    EMIFA_temp |= 0x00055CA8;
    EMIFA_RSET(SDEXT, EMIFA_temp);

    /*
        Do some basic EMIFB setup so the platformBus can be configured
    */

    // GBLCTL
    EMIFB_temp = EMIFB_RGET(GBLCTL);
    EMIFB_temp &= 0xFFF0D007;
    EMIFB_temp |= 0x000920A0;
    EMIFB_RSET(GBLCTL, EMIFB_temp);

    // CECTL0-3
    EMIFB_RSET( CECTL0, 0x13410D10); // No reserved bits, just write a value
    EMIFB_RSET( CECTL1, 0x33514D10);
    EMIFB_RSET( CECTL2, 0x33514D10);
    EMIFB_RSET( CECTL3, 0x11814610);

	EMIFA_temp = EMIFA_RGET(SDCTL);
    EMIFA_temp &= 0x80000FFE;
    switch(SDRAMSize)
    {
        case 32:
            EMIFA_temp |= 0x57116000;
            EMIFA_RSET(SDCTL, EMIFA_temp);
            break;
        case 128:
        	EMIFA_temp |= 0x53116000;
        	EMIFA_RSET(SDCTL, EMIFA_temp);
            break;
        case 256:
        	EMIFA_temp |= 0x5B116000;
            EMIFA_RSET(SDCTL, EMIFA_temp);
            break;
        case 512:
            EMIFA_RSET(CECTL1, 0xFFFFFFDF);
            EMIFA_temp |= 0x5B116000;
            EMIFA_RSET(SDCTL, EMIFA_temp);
            break;
        default:
            // We should never actually get here, unless the
            // EEPROM is corrupt.  In that case, load the
            // 32MB values, because they are the safest defaults.
            EMIFA_temp |= 0x57116000;
            EMIFA_RSET(SDCTL, EMIFA_temp);
            break;
    }

    // Setup platformBus and put it into Reset
    // PlatformBus must be in Reset for the bus speed to be changed.
    pbctl_temp = UMISC_RGET(PBCTL0);
    UMISC_RSET(PBCTL1, 0x0100);

	UMISC_RSET(PBCTL0, 0x8220);
	
    /*
        Change platformBus speed to 50 MHz

        We must do this without touching any of the reserved bits in the
        GBLCTL register.  Modifiying the reserved bits can crash the 1GHz
        version of the DSP.
    */

    // Read in the current EMIFB GBLCTL register
    PBus_temp = EMIFB_RGET(GBLCTL);

    // Wipe out all the bits we want to change, without affecting any reserved bits.
    PBus_temp &= 0xFFF0D007;

    // Set the bits
    PBus_temp |= 0x000520A0;

    // Write the modified value
    EMIFB_RSET(GBLCTL, PBus_temp);



    /*
        The platformBus must be held in reset for 50us after a speed
        change.  Since there is no udelay() function in the DSP's C runtime
        library, we have to use one of the onboard timers for the delay.

        The timers count based on the DSP clock speed.  Therefore, we
        can't delay for a fixed number of timer ticks.  We already know
        the DSP frequency in MHz, so we can use it to calculate the
        number of timer ticks.

        This value has to be divided by 8, because the timers use 1/8 the
        DSP clock.
    */
    Timer_Tick_Count = ((BSL_boardDescriptor.dspNomSpeed * 50) / 8);

    hTimer = TIMER_open(TIMER_DEVANY, TIMER_OPEN_RESET);

    TIMER_reset(hTimer);

    // This will configure and start the timer in one operation.
    TIMER_configArgs(hTimer, 0x000002C0, 0xFFFFFFFF, 0x00000000);

    while( TIMER_getCount(hTimer) < Timer_Tick_Count);

    // Bring platformBus out of reset
    UMISC_RSET(PBCTL0, (pbctl_temp & 0x40FC)|(0x0220 & ~0x40FC));


    // Delay for another 50us to make sure the platformBus made it all the
    // way out of reset before returning.
    TIMER_reset(hTimer);
    TIMER_configArgs(hTimer, 0x000002C0, 0xFFFFFFFF, 0x00000000);
    while( TIMER_getCount(hTimer) < Timer_Tick_Count);


    // Reset and close the timer when we're done, so it is restored to a
    // known state.
    TIMER_reset(hTimer);
    TIMER_close(hTimer);

}


/******************************************************************************\
* static typedef declarations
\******************************************************************************/


/******************************************************************************\
* static function declarations
\******************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

// Initialization functions of COMM and FLASH modules
extern far void COMM_init();    // defined in bsl_comm.c
extern far void FLASH_init();   // defined in bsl_flash.c

// Callback Interrupt Service Routine of COMM and FLASH modules
extern far void COMM_ISR_CB();  // defined in bsl_comm.c
extern far void FLASH_ISR_CB(); // defined in bsl_flash.c

#ifdef __cplusplus
}
#endif  // extern "C" {


/******************************************************************************\
* static variable definitions
\******************************************************************************/


/******************************************************************************\
* static function definitions
\******************************************************************************/

interrupt void BSL_ISR_DISPATCHER()
{
    // In this ISR, there are assembly instructions whose results depend on
    // AMR and SAT. That is, the AMR and SAT have to be saved and restored.
    Uint32  temp_AMR, temp_SAT; // to save the AMR and SAT

    // save AMR and SAT
    SAVE_AMR(temp_AMR);
    SAVE_SAT(temp_SAT);

    do
    {
        if( UINT_FGETSQ( STATUS, P2LDBIA, ACTIVE ) ) COMM_ISR_CB();
        if( UINT_FGETSQ( STATUS, FRYBYIA, ACTIVE ) ) FLASH_ISR_CB();
    }
    while( UINT_RGET(STATUS) & (_UINT_STATUS_P2LDBIA_ACTIVE_SV | _UINT_STATUS_FRYBYIA_ACTIVE_SV) );

    // restore AMR and SAT
    RESTORE_AMR(temp_AMR);
    RESTORE_SAT(temp_SAT);
}


/******************************************************************************\
*                        G L O B A L   S E C T I O N
\******************************************************************************/


/******************************************************************************\
* global variable definitions
\******************************************************************************/

BSL_BoardDescriptor BSL_boardDescriptor;


/******************************************************************************\
* global function definitions
\******************************************************************************/

/*----------------------------------------------------------------------------*/
void BSL_init()
{
    //------------------------------------------------------
    // initializing of the DSP interrupt conditions
    //------------------------------------------------------
    IER = 0x0003;   // enable Reset and NMI only
    ICR = 0xFFFF;   // clear all pending ITs
    CSR |= 1;       // enable Global Interrupt Enable (GIE)

    //------------------------------------------------------
    // initializing of the Chip Support Library
    //------------------------------------------------------
    CSL_init();

    //------------------------------------------------------
    // reading HW information from the EEPROM
    //------------------------------------------------------

    // per-initializing EMIFB for the fastest board to reach the FPGA registers
    EMIFB_RSET( GBLCTL, CFG_EMIFB_GBLCTL_600 );
    EMIFB_RSET( CECTL3, CFG_EMIFB_CECTL3_600 );

    // set "DSP is in use" flag
    UMISC_RFSETS( DHCOMM, DSPINUSE, INUSE );

    // wait for EEPROM ready
    while( ! (PCI_FGET(RSTSRC,CFGDONE)) );

    // McBSP2 override for EEPROM access
    UMISC_switchToEEPROM();

    // reading HW information from the EEPROM
    BSL_boardDescriptor.dspNomSpeed = (Uint32)PCI_eepromRead(EEVAR_DSPNOMSP_OFFS);
    BSL_boardDescriptor.flashSize   = (Uint32)PCI_eepromRead(EEVAR_FLASHSZ_OFFS);
    BSL_boardDescriptor.sdramSize   = (Uint32)PCI_eepromRead(EEVAR_SDRAMSZ_OFFS);

    // switch to AUTO mode(McBSP is active except for a few milliseconds after PCI reset)
    UMISC_switchToAuto();

    //BSL_boardDescriptor.dspNomSpeed   = 600;
    //BSL_boardDescriptor.flashSize = 4;
    //BSL_boardDescriptor.sdramSize = 128;

    SPM6400_EMIF_INIT(BSL_boardDescriptor.sdramSize);

    //------------------------------------------------------
    // initializing Communication and Flash Controller
    // after the initialization of EMIF
    //------------------------------------------------------

    IRQ_disable(IRQ_EVT_EXTINT7);

    // ExtInt7 must be a rising edge sensitive pin (EXTPOL.XIP7 = 0)
    IRQ_RSET( EXTPOL, IRQ_RGET(EXTPOL) & (~0x8) );

    // Disable every sources for ExtInt7 pin
    // The proper sources will be set by the COMM_init() and by the FLASH_init()
    UINT_RSET( EIT7SRC, 0 );

    COMM_init();
    FLASH_init();

    IRQ_clear(IRQ_EVT_EXTINT7);
    IRQ_enable(IRQ_EVT_EXTINT7);

    //------------------------------------------------------
    // initializing PCI Bus peripheral Controller
    //------------------------------------------------------

    IRQ_disable(IRQ_EVT_DSPINT);

    PCIBUS_init();

    // enables DSPINT's interrupt on Int13 by default
    // for the PCI peripheral interrupts
    IRQ_clear(IRQ_EVT_DSPINT);
    IRQ_enable(IRQ_EVT_DSPINT);

}


/*----------------------------------------------------------------------------*/

/******************************************************************************\
* End of bsl_bsl.c
\******************************************************************************/