?? xspcore.vhd
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--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project: Full-Speed USB 1.1 Function Controller
-- File: xspCORE.vhd
-- Description: XSP-010 board, FPGA core logic.
-- Version: FB, 2000jul29
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xspCORE is
port(
OSC: in STD_LOGIC;
RD: in STD_LOGIC;
WR: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (15 downto 0);
DIN: in STD_LOGIC_VECTOR (7 downto 0);
PC_D: in STD_LOGIC_VECTOR (7 downto 0);
DDRV: out STD_LOGIC;
RST: out STD_LOGIC;
XTAL: out STD_LOGIC;
DOUT: out STD_LOGIC_VECTOR (7 downto 0);
S: out STD_LOGIC_VECTOR (6 downto 0);
P1: inout STD_LOGIC_VECTOR (7 downto 0)
);
end xspCORE;
--------------------------------------------------------------------------------
architecture BHV of xspCORE is
---- Signal declarations used on the diagram ----
signal DI : STD_LOGIC_VECTOR (3 downto 1);
signal NK : STD_LOGIC_VECTOR (3 downto 1);
signal ST : STD_LOGIC_VECTOR (3 downto 1);
signal TG : STD_LOGIC_VECTOR (3 downto 1);
signal TX : STD_LOGIC_VECTOR (7 downto 0);
signal BUS897 : STD_LOGIC_VECTOR (2 downto 0);
signal BUS901 : STD_LOGIC_VECTOR (7 downto 0);
signal BUS905 : STD_LOGIC_VECTOR (7 downto 0);
signal BUS909 : STD_LOGIC_VECTOR (7 downto 0);
signal BUS913 : STD_LOGIC_VECTOR (7 downto 0);
signal BUS917 : STD_LOGIC_VECTOR (6 downto 0);
signal NET1855 : STD_LOGIC;
signal NET1859 : STD_LOGIC;
signal NET1863 : STD_LOGIC;
signal NET1867 : STD_LOGIC;
signal NET1871 : STD_LOGIC;
signal NET390 : STD_LOGIC;
signal NET921 : STD_LOGIC;
signal NET925 : STD_LOGIC;
signal NET929 : STD_LOGIC;
---- Component declarations -----
component usbEP0
generic(
epin_mask : bit_vector(3 downto 0) := "0001";
episo_mask : bit_vector(3 downto 0) := "0000";
epout_mask : bit_vector(3 downto 0) := "0001";
epsetup_mask : bit_vector(3 downto 0) := "0001"
);
port (
clk12 : in STD_LOGIC;
clk48 : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (3 downto 1);
nak : in STD_LOGIC_VECTOR (3 downto 1);
rst : in STD_LOGIC;
stall : in STD_LOGIC_VECTOR (3 downto 1);
togglein : in STD_LOGIC_VECTOR (3 downto 1);
txd : in STD_LOGIC_VECTOR (7 downto 0);
uc_adx : in STD_LOGIC_VECTOR (2 downto 0);
uc_ctrl : in STD_LOGIC_VECTOR (7 downto 0);
uc_dadx : in STD_LOGIC_VECTOR (6 downto 0);
uc_dwr : in STD_LOGIC_VECTOR (7 downto 0);
uc_wradx : in STD_LOGIC;
uc_wrctrl : in STD_LOGIC;
uc_wren : in STD_LOGIC;
urx0 : in STD_LOGIC;
urxd : in STD_LOGIC;
clk12o : out STD_LOGIC;
in_trac : out STD_LOGIC_VECTOR (3 downto 0);
out_trac : out STD_LOGIC_VECTOR (3 downto 0);
rxd : out STD_LOGIC_VECTOR (7 downto 0);
rxen : out STD_LOGIC;
rxfrm : out STD_LOGIC_VECTOR (10 downto 0);
setup_trac : out STD_LOGIC_VECTOR (3 downto 0);
sof_trac : out STD_LOGIC;
txen : out STD_LOGIC;
uc_drd : out STD_LOGIC_VECTOR (7 downto 0);
uc_status : out STD_LOGIC_VECTOR (7 downto 0);
utx0 : out STD_LOGIC;
utxd : out STD_LOGIC;
utxoe : out STD_LOGIC
);
end component;
component xspCLK
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
clko : out STD_LOGIC;
rsto : out STD_LOGIC
);
end component;
component xspLED
port (
A : in STD_LOGIC_VECTOR (15 downto 0);
DWR : in STD_LOGIC_VECTOR (7 downto 0);
WR : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
component xspPHY
port (
utx0 : in STD_LOGIC;
utxd : in STD_LOGIC;
utxoe : in STD_LOGIC;
vm : in STD_LOGIC;
vp : in STD_LOGIC;
fse0 : out STD_LOGIC;
oe : out STD_LOGIC;
urx0 : out STD_LOGIC;
urxd : out STD_LOGIC;
vpo : out STD_LOGIC
);
end component;
component xspUSB
port (
A : in STD_LOGIC_VECTOR (15 downto 0);
DIN : in STD_LOGIC_VECTOR (7 downto 0);
RD : in STD_LOGIC;
WR : in STD_LOGIC;
uc_drd : in STD_LOGIC_VECTOR (7 downto 0);
uc_status : in STD_LOGIC_VECTOR (7 downto 0);
DDRV : out STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (7 downto 0);
uc_adx : out STD_LOGIC_VECTOR (2 downto 0);
uc_ctrl : out STD_LOGIC_VECTOR (7 downto 0);
uc_dadx : out STD_LOGIC_VECTOR (6 downto 0);
uc_dwr : out STD_LOGIC_VECTOR (7 downto 0);
uc_wradx : out STD_LOGIC;
uc_wrctrl : out STD_LOGIC;
uc_wren : out STD_LOGIC
);
end component;
begin
---- User defined VHDL code ----
----- Statement0 ----
P1<= (others=> 'Z');
----- Statement1 ----
tx<= (others=> 'Z');
nk<= (others=> '0');
st<= (others=> '0');
tg<= (others=> '0');
di<= (others=> '0');
---- Component instantiations ----
Uclk : xspCLK
port map(
clk => OSC,
clko => XTAL,
rst => PC_D(0),
rsto => RST
);
Uglue : xspUSB
port map(
A => A,
DDRV => DDRV,
DIN => DIN,
DOUT => DOUT,
RD => RD,
WR => WR,
uc_adx => BUS897,
uc_ctrl => BUS909,
uc_dadx => BUS917,
uc_drd => BUS901,
uc_dwr => BUS905,
uc_status => BUS913,
uc_wradx => NET925,
uc_wrctrl => NET921,
uc_wren => NET929
);
Uled : xspLED
port map(
A => A,
DWR => DIN,
LED => S,
WR => WR
);
Uphy : xspPHY
port map(
fse0 => P1(3),
oe => P1(4),
urx0 => NET1859,
urxd => NET1855,
utx0 => NET1867,
utxd => NET1863,
utxoe => NET1871,
vm => P1(1),
vp => P1(0),
vpo => P1(2)
);
Uusb : usbEP0
generic map (
epin_mask => "0001",
episo_mask => "0000",
epout_mask => "0001",
epsetup_mask => "0001"
)
port map(
clk12 => NET390,
clk12o => NET390,
clk48 => OSC,
datain => di,
nak => nk,
rst => PC_D(0),
stall => st,
togglein => tg,
txd => tx,
uc_adx => BUS897,
uc_ctrl => BUS909,
uc_dadx => BUS917,
uc_drd => BUS901,
uc_dwr => BUS905,
uc_status => BUS913,
uc_wradx => NET925,
uc_wrctrl => NET921,
uc_wren => NET929,
urx0 => NET1859,
urxd => NET1855,
utx0 => NET1867,
utxd => NET1863,
utxoe => NET1871
);
end BHV;
--------------------------------------------------------------------------------
-- end of file
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