#ifndef _8019AS_H
#define _8019AS_H 

#include "sys.h"
///////////////////////////////////////////////////////
ioport unsigned port9300;
ioport unsigned port9301;
ioport unsigned port9302;
ioport unsigned port9303;
ioport unsigned port9304;
ioport unsigned port9305;
ioport unsigned port9306;
ioport unsigned port9307;
ioport unsigned port9308;
ioport unsigned port9309;
ioport unsigned port930a;
ioport unsigned port930b;
ioport unsigned port930c;
ioport unsigned port930d;
ioport unsigned port930e;
ioport unsigned port930f;
ioport unsigned port9310;
ioport unsigned port9318;
ioport unsigned port9322;




ioport unsigned port800d;//net reset io port
//////////////////////////////////////////////////////	
#define NIC_RCV_MIN_PG		0x4C
#define NIC_RCV_MAX_PG	    0x7F
#define NIC_TX_MIN_PG		0x40
#define NIC_TX_MAX_PG		0x4B
#define PgSelect(page)	  	port9300=(port9300 & 0x3f) | (page<<6)

#define REMOTE_DMA_PORT		0x10	/* NIC internal adress */
#define REG_RESET		0x18	/* reset Reg 0x18-1f */
/* Some generic ethernet register configurations. */
#define RTL8019AS_TX_IRQ_MASK	0x0a	/* For register PG0_ISR */
#define RTL8019AS_RX_IRQ_MASK	0x5
#define RTL8019AS_RXCONFIG	0x4	/* PG0_RXCR: broadcasts, no multicast,errors */
#define RTL8019AS_RXOFF		0x20	/* PG0_RXCR: Accept no packets */
#define RTL8019AS_TXCONFIG	0x00	/* PG0_TXCR: Normal transmit mode */
#define RTL8019AS_TXOFF		0x02	/* PG0_TXCR: Transmitter off */

/*  Register accessed at PG0123_CMD, the RTL8019AS base addr.  */
#define CMD_STOP		0x01	/* Stop and reset the chip */
#define CMD_START		0x02	/* Start the chip, clear reset */
#define CMD_TRANS		0x04	/* Transmit a frame */
#define CMD_RREAD		0x08	/* Remote read */
#define CMD_RWRITE		0x10	/* Remote write  */
#define CMD_NODMA		0x20	/* Remote DMA */
#define CMD_PAGE0		0x00	/* Select page chip registers */
#define CMD_PAGE1		0x40	/* using the two high-order bits */
#define CMD_PAGE2		0x80	/* Page 3 is invalid. */

#define PG0123_CMD	port9300	/* The command register (for all pages) */
/* Page 0 register offsets. */
#define PG0_CLDALO	port9301		/* Low byte of current local dma addr  RD */
#define PG0_PSTART	port9301		/* Starting page of ring bfr WR */
#define PG0_CLDAHI	port9302		/* High byte of current local dma addr  RD */
#define PG0_PSTOP	port9302		/* Ending page +1 of ring bfr WR */
#define PG0_BNDRY	port9303		/* Boundary page of ring bfr RD WR */
#define PG0_TSR	    port9304		/* Transmit status reg RD */
#define PG0_TPSR	port9304		/* Transmit starting page WR */
#define PG0_NCR		port9305		/* Number of collision reg RD */
#define PG0_TBCRLO	port9305		/* Low  byte of tx byte count WR */
#define PG0_FIFO	port9306		/* FIFO RD */
#define PG0_TBCRHI	port9306		/* High byte of tx byte count WR */
#define PG0_ISR		port9307		/* Interrupt status reg RD WR */
#define PG0_CRDALO	port9308		/* 0,low byte of current remote dma address RD */
#define PG0_RSARLO	port9308		/* 0,Remote start address reg 0 */
#define PG0_CRDAHI	port9309		/* 1,high byte, current remote dma address RD */
#define PG0_RSARHI	port9309		/* 1,Remote start address reg 1 */
#define PG0_RBCRLO	port930a		/* 0,Remote byte count reg WR */
#define PG0_RBCRHI	port930b		/* 1,Remote byte count reg WR */
#define PG0_RSR		port930c		/* rx status reg RD */
#define PG0_RCR		port930c		/* RX configuration reg WR */
#define PG0_TCR		port930d		/* TX configuration reg WR */
#define PG0_COUNTER0	port930d		/* Rcv alignment error counter RD */
#define PG0_DCR		port930e		/* Data configuration reg WR */
#define PG0_COUNTER1	port930e		/* Rcv CRC error counter RD */
#define PG0_IMR		port930f		/* Interrupt mask reg WR */
#define PG0_COUNTER2	port930f		/* Rcv missed frame error counter RD */


/* Page 1 register offsets. */
#define PG1_PAR0	port9301		/* Phisical Address Reg,RW */
#define PG1_PAR1	port9302
#define PG1_PAR2	port9303
#define PG1_PAR3	port9304
#define PG1_PAR4	port9305
#define PG1_PAR5	port9306

#define PG1_CURR	port9307		/* Current Page Reg,RW */

#define PG1_MAR0	port9308		/* Multicast Address Reg,RW */
#define PG1_MAR1	port9309
#define PG1_MAR2	port930a
#define PG1_MAR3	port930b
#define PG1_MAR4	port930c
#define PG1_MAR5	port930d
#define PG1_MAR6	port930e
#define PG1_MAR7	port930f


/* Page 2 register offsets. */
#define PG2_PSTART	port9301		/* Page Start Reg,RD */
#define PG2_PSTOP	port9302		/* Page Stop Reg,RD */
#define PG2_TPSR	port9304		/* Transmit Page Start Reg,RD */
#define PG2_RCR		port930c		/* Receive Configuration Reg,RD */
#define PG2_TCR		port930d		/* Tx Cfg Reg,RD */
#define PG2_DCR		port930e		/* Data Cfg Reg,Rd */
#define PG2_IMR		port930f		/* Interrupt Mask Reg,RD */


/* Page 3 register offsets. */
#define PG3_9346CR	port9301		/* 9346 Cmd Reg,RW except Bit0=R */
/* |EEM1-0(7-6)|RSVD(5-4)|EECS(3)EESK(2)|EEDI(1)|EEDO(0)| */
#define PG3_BPAGE	port9302		/* BROM Page Reg,RW */

#define PG3_CONFIG0	port9303		/* RTL8019AS Cfg Reg 0 */
/* |VERID(7-6)|AUI(5)|PNPJP(4)|JP(3)|BNC(2)|ALWAY0(1-0)| */
#define PG3_CONFIG1	port9304        /* Cfg Reg 1 ,R except Bit7=RW */
/* |IRQEN(7)|IRQS2-0(6-4)|IOS3-0(3-0)| */
#define PG3_CONFIG2	port9305		/* Cfg Reg 2,R except Bit[7:5]=RW */
/* |PL1-0(7-6)|BSELB(5)|BS4-0(4-0)| */ 
#define PG3_CONFIG3	port9306        /* Cfg Reg 3,R except Bit[2:1]=RW) */
/* |PNP(7)|FUDUP(6)|LEDS1-0(5-4)|RSVD(3)|SLEEP(2)|PWRDN(1)|ACTIVEB(0)| */

#define PG3_TEST	port9307		/* no use */
#define PG3_CSNSAV	port9308		/* CSN Save Reg,RD */
#define PG3_HLTCLK	port9309		/* Halt Clock Reg,W */
#define PG3_INTR	port930b		/* Interrupt Reg,Rreflect the ISA bus states of INT7-0
					   pins*/
#define PG3_FMWP	port930c		/* Flash Memory Write Protect Reg,W */
#define PG3_CONFIG4	port930d


/*  Register accessed at PG0123_CR, the 8019as control addr.  */
#define CR_STOP			0x01	/* Stop and reset the chip */
#define CR_START		0x02	/* Start the chip, clear reset */
#define CR_TRANS		0x04	/* Transmit a frame */
#define CR_RREAD		0x08	/* Remote read */
#define CR_RWRITE		0x10	/* Remote write  */
#define CR_NODMA		0x20	/* Remote DMA */
#define CR_PAGE0		0x00	/* Select page chip registers */
#define CR_PAGE1		0x40	/* using the two high-order bits */
#define CR_PAGE2		0x80	/* Page 3 is invalid. */


/* Bits in PG0_ISR */
/*
 * |RST(7)|RDC(6)|CNT(5)|OVW(4)|TXE(3)|RXE(2)|PTX(1)|PRX(0)|
*/
#define PG0_ISR_PRX		0x01	/* Receiver, no error */
#define PG0_ISR_PTX		0x02	/* Transmitter, no error */
#define PG0_ISR_RX_ERR		0x04	/* Receiver, with error */
#define PG0_ISR_TX_ERR		0x08	/* Transmitter, with error */
#define PG0_ISR_OVER		0x10	/* Receiver overwrote the ring */
#define PG0_ISR_COUNTERS	0x20	/* Counters need emptying */
#define PG0_ISR_RDC		0x40	/* remote dma complete */
#define PG0_ISR_RESET		0x80	/* Reset completed */
#define PG0_ISR_ALL		0x3f	/* Interrupts we will enable */

/* Bits in PG0_DCR - Data config register */
/*
 * |RSV(7),A1|FT1,FT0(6-5)|ARM(4)|LS(3)|LAS(2)|BOS(1)|WTS(0)|	A:allways
 *
*/
#define PG0_DCR_WTS		0x01	/* word transfer mode selection */

/* Bits in received packet status byte and PG0_RSR*/
#define PG0_RSR_RXOK		0x01	/* Received a good packet */
#define PG0_RSR_CRC		0x02	/* CRC error */
#define PG0_RSR_FAE		0x04	/* frame alignment error */
#define PG0_RSR_FO		0x08	/* FIFO overrun */
#define PG0_RSR_MPA		0x10	/* missed pkt */
#define PG0_RSR_PHY		0x20	/* physical/multicast address */
#define PG0_RSR_DIS		0x40	/* receiver disable. set in monitor mode */
#define PG0_RSR_DEF		0x80	/* deferring */

/* Transmitted packet status, PG0_TSR. */
#define PG0_TSR_PTX		0x01	/* Packet transmitted without error */
#define PG0_TSR_ND		0x02	/* The transmit wasn't deferred. */
#define PG0_TSR_COL		0x04	/* The transmit collided at least once. */
#define PG0_TSR_ABT		0x08	/* The transmit collided 16 times, and was deferred. */
#define PG0_TSR_CRS		0x10	/* The carrier sense was lost. */
#define PG0_TSR_FU		0x20	/* A "FIFO underrun" occurred during transmit. */
#define PG0_TSR_CDH		0x40	/* The collision detect "heartbeat" signal was lost. */
#define PG0_TSR_OWC		0x80	/* There was an out-of-window collision. */

static void WaitRDMAOperationDone(void);
void NIC_TxFrame(void);
void NIC_RcvFrame(void);
u16_t SendData(u16_t *pappdata,u16_t appdatalen);
#endif /* #define _8019AS_H */