(match_operand:QI 2 "general_operand" "g")))]  ""  "mulb %2,%0")(define_insn "umulsidi3"  [(set (match_operand:DI 0 "general_operand" "=g")	(umult:DI (match_operand:SI 1 "general_operand" "0")		  (match_operand:SI 2 "general_operand" "rmn")))]  ""  "meid %2,%0");;- Divide instructions.(define_insn "divdf3"  [(set (match_operand:DF 0 "general_operand" "=fm")	(div:DF (match_operand:DF 1 "general_operand" "0")		(match_operand:DF 2 "general_operand" "fmF")))]  "TARGET_32081"  "divl %2,%0")(define_insn "divsf3"  [(set (match_operand:SF 0 "general_operand" "=fm")	(div:SF (match_operand:SF 1 "general_operand" "0")		(match_operand:SF 2 "general_operand" "fmF")))]  "TARGET_32081"  "divf %2,%0")(define_insn "divsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(div:SI (match_operand:SI 1 "general_operand" "0")		(match_operand:SI 2 "general_operand" "rmn")))]  ""  "quod %2,%0")(define_insn "divhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(div:HI (match_operand:HI 1 "general_operand" "0")		(match_operand:HI 2 "general_operand" "g")))]  ""  "quow %2,%0")(define_insn "divqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(div:QI (match_operand:QI 1 "general_operand" "0")		(match_operand:QI 2 "general_operand" "g")))]  ""  "quob %2,%0")(define_insn "udivsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)		 (match_operand:SI 2 "general_operand" "rmn")))]  ""  "*{  operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);  return \"deid %2,%0\;movd %1,%0\";}")(define_insn "udivhi3"  [(set (match_operand:HI 0 "register_operand" "=r")	(udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)		 (match_operand:HI 2 "general_operand" "g")))]  ""  "*{  operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);  return \"deiw %2,%0\;movw %1,%0\";}")(define_insn "udivqi3"  [(set (match_operand:QI 0 "register_operand" "=r")	(udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)		 (match_operand:QI 2 "general_operand" "g")))]  ""  "*{  operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);  return \"deib %2,%0\;movb %1,%0\";}");; Remainder instructions.(define_insn "modsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(mod:SI (match_operand:SI 1 "general_operand" "0")		(match_operand:SI 2 "general_operand" "rmn")))]  ""  "remd %2,%0")(define_insn "modhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(mod:HI (match_operand:HI 1 "general_operand" "0")		(match_operand:HI 2 "general_operand" "g")))]  ""  "remw %2,%0")(define_insn "modqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(mod:QI (match_operand:QI 1 "general_operand" "0")		(match_operand:QI 2 "general_operand" "g")))]  ""  "remb %2,%0")(define_insn "umodsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)		 (match_operand:SI 2 "general_operand" "rmn")))]  ""  "deid %2,%0")(define_insn "umodhi3"  [(set (match_operand:HI 0 "register_operand" "=r")	(umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)		 (match_operand:HI 2 "general_operand" "g")))]  ""  "deiw %2,%0")(define_insn "umodqi3"  [(set (match_operand:QI 0 "register_operand" "=r")	(umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)		 (match_operand:QI 2 "general_operand" "g")))]  ""  "deib %2,%0"); This isn't be usable in its current form.;(define_insn "udivmoddisi4";  [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1);	(udiv:SI (match_operand:DI 1 "general_operand" "0");		 (match_operand:SI 2 "general_operand" "rmn")));   (set (subreg:SI (match_dup 0) 0);	(umod:SI (match_dup 1) (match_dup 2)))];  "";  "deid %2,%0");;- Logical Instructions: AND(define_insn "andsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(and:SI (match_operand:SI 1 "general_operand" "%0")		(match_operand:SI 2 "general_operand" "rmn")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT)    {      if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)	{	  if (INTVAL (operands[2]) == 0xffffff00)	    return \"movqb %$0,%0\";	  else	    {	      operands[2] = gen_rtx (CONST_INT, VOIDmode,				     INTVAL (operands[2]) & 0xff);	      return \"andb %2,%0\";	    }	}      if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)        {	  if (INTVAL (operands[2]) == 0xffff0000)	    return \"movqw %$0,%0\";	  else	    {	      operands[2] = gen_rtx (CONST_INT, VOIDmode,				     INTVAL (operands[2]) & 0xffff);	      return \"andw %2,%0\";	    }	}    }  return \"andd %2,%0\";}")(define_insn "andhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(and:HI (match_operand:HI 1 "general_operand" "%0")		(match_operand:HI 2 "general_operand" "g")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT      && (INTVAL (operands[2]) | 0xff) == 0xffffffff)    {      if (INTVAL (operands[2]) == 0xffffff00)	return \"movqb %$0,%0\";      else	{	  operands[2] = gen_rtx (CONST_INT, VOIDmode,				 INTVAL (operands[2]) & 0xff);	  return \"andb %2,%0\";	}    }  return \"andw %2,%0\";}")(define_insn "andqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(and:QI (match_operand:QI 1 "general_operand" "%0")		(match_operand:QI 2 "general_operand" "g")))]  ""  "andb %2,%0")(define_insn "andcbsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(and:SI (match_operand:SI 1 "general_operand" "0")		(not:SI (match_operand:SI 2 "general_operand" "rmn"))))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT)    {      if ((INTVAL (operands[2]) & 0xffffff00) == 0)	return \"bicb %2,%0\";      if ((INTVAL (operands[2]) & 0xffff0000) == 0)	return \"bicw %2,%0\";    }  return \"bicd %2,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))		(match_operand:SI 2 "general_operand" "0")))]  ""  "*{  if (GET_CODE (operands[1]) == CONST_INT)    {      if ((INTVAL (operands[1]) & 0xffffff00) == 0)	return \"bicb %1,%0\";      if ((INTVAL (operands[1]) & 0xffff0000) == 0)	return \"bicw %1,%0\";    }  return \"bicd %1,%0\";}")(define_insn "andcbhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(and:HI (match_operand:HI 1 "general_operand" "0")		(not:HI (match_operand:HI 2 "general_operand" "g"))))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT      && (INTVAL (operands[2]) & 0xffffff00) == 0)    return \"bicb %2,%0\";  return \"bicw %2,%0\";}")(define_insn ""  [(set (match_operand:HI 0 "general_operand" "=g")	(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))		(match_operand:HI 2 "general_operand" "0")))]  ""  "*{  if (GET_CODE (operands[1]) == CONST_INT      && (INTVAL (operands[1]) & 0xffffff00) == 0)    return \"bicb %1,%0\";  return \"bicw %1,%0\";}")(define_insn "andcbqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(and:QI (match_operand:QI 1 "general_operand" "0")		(not:QI (match_operand:QI 2 "general_operand" "g"))))]  ""  "bicb %2,%0")(define_insn ""  [(set (match_operand:QI 0 "general_operand" "=g")	(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))		(match_operand:QI 2 "general_operand" "0")))]  ""  "bicb %1,%0");;- Bit set instructions.(define_insn "iorsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(ior:SI (match_operand:SI 1 "general_operand" "%0")		(match_operand:SI 2 "general_operand" "rmn")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT) {    if ((INTVAL (operands[2]) & 0xffffff00) == 0)      return \"orb %2,%0\";    if ((INTVAL (operands[2]) & 0xffff0000) == 0)      return \"orw %2,%0\";  }  return \"ord %2,%0\";}")(define_insn "iorhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(ior:HI (match_operand:HI 1 "general_operand" "%0")		(match_operand:HI 2 "general_operand" "g")))]  ""  "*{  if (GET_CODE(operands[2]) == CONST_INT &&      (INTVAL(operands[2]) & 0xffffff00) == 0)    return \"orb %2,%0\";  return \"orw %2,%0\";}")(define_insn "iorqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(ior:QI (match_operand:QI 1 "general_operand" "%0")		(match_operand:QI 2 "general_operand" "g")))]  ""  "orb %2,%0");;- xor instructions.(define_insn "xorsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(xor:SI (match_operand:SI 1 "general_operand" "%0")		(match_operand:SI 2 "general_operand" "rmn")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT) {    if ((INTVAL (operands[2]) & 0xffffff00) == 0)      return \"xorb %2,%0\";    if ((INTVAL (operands[2]) & 0xffff0000) == 0)      return \"xorw %2,%0\";  }  return \"xord %2,%0\";}")(define_insn "xorhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(xor:HI (match_operand:HI 1 "general_operand" "%0")		(match_operand:HI 2 "general_operand" "g")))]  ""  "*{  if (GET_CODE(operands[2]) == CONST_INT &&      (INTVAL(operands[2]) & 0xffffff00) == 0)    return \"xorb %2,%0\";  return \"xorw %2,%0\";}")(define_insn "xorqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(xor:QI (match_operand:QI 1 "general_operand" "%0")		(match_operand:QI 2 "general_operand" "g")))]  ""  "xorb %2,%0")(define_insn "negdf2"  [(set (match_operand:DF 0 "general_operand" "=fm<")	(neg:DF (match_operand:DF 1 "general_operand" "fmF")))]  "TARGET_32081"  "negl %1,%0")(define_insn "negsf2"  [(set (match_operand:SF 0 "general_operand" "=fm<")	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]  "TARGET_32081"  "negf %1,%0")(define_insn "negsi2"  [(set (match_operand:SI 0 "general_operand" "=g<")	(neg:SI (match_operand:SI 1 "general_operand" "rmn")))]  ""  "negd %1,%0")(define_insn "neghi2"  [(set (match_operand:HI 0 "general_operand" "=g<")	(neg:HI (match_operand:HI 1 "general_operand" "g")))]  ""  "negw %1,%0")(define_insn "negqi2"  [(set (match_operand:QI 0 "general_operand" "=g<")	(neg:QI (match_operand:QI 1 "general_operand" "g")))]  ""  "negb %1,%0")(define_insn "one_cmplsi2"  [(set (match_operand:SI 0 "general_operand" "=g<")	(not:SI (match_operand:SI 1 "general_operand" "rmn")))]  ""  "comd %1,%0")(define_insn "one_cmplhi2"  [(set (match_operand:HI 0 "general_operand" "=g<")	(not:HI (match_operand:HI 1 "general_operand" "g")))]  ""  "comw %1,%0")(define_insn "one_cmplqi2"  [(set (match_operand:QI 0 "general_operand" "=g<")	(not:QI (match_operand:QI 1 "general_operand" "g")))]  ""  "comb %1,%0");; arithmetic left and right shift operations(define_insn "ashlsi3"  [(set (match_operand:SI 0 "general_operand" "=g,g")	(ashift:SI (match_operand:SI 1 "general_operand" "r,0")		   (match_operand:SI 2 "general_operand" "I,rmn")))]  ""  "* return output_shift_insn (operands);")(define_insn "ashlhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(ashift:HI (match_operand:HI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "rmn")))]  ""  "*{ if (GET_CODE (operands[2]) == CONST_INT)    if (INTVAL (operands[2]) == 1)      return \"addw %0,%0\";    else if (INTVAL (operands[2]) == 2)      return \"addw %0,%0\;addw %0,%0\";  return \"ashw %2,%0\";}")(define_insn "ashlqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(ashift:QI (match_operand:QI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "rmn")))]  ""  "*{ if (GET_CODE (operands[2]) == CONST_INT)    if (INTVAL (operands[2]) == 1)      return \"addb %1,%0\";    else if (INTVAL (operands[2]) == 2)      return \"addb %1,%0\;addb %0,%0\";  return \"ashb %2,%0\";}");; Arithmetic right shift on the 32k works by negating the shift count.(define_expand "ashrsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(ashift:SI (match_operand:SI 1 "general_operand" "g")		   (match_operand:SI 2 "general_operand" "g")))]  ""  "{  operands[2] = negate_rtx (SImode, operands[2]);}")(define_expand "ashrhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(ashift:HI (match_operand:HI 1 "general_operand" "g")		   (match_operand:SI 2 "general_operand" "g")))]  ""  "{  operands[2] = negate_rtx (SImode, operands[2]);}")(define_expand "ashrqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(ashift:QI (match_operand:QI 1 "general_operand" "g")		   (match_operand:SI 2 "general_operand" "g")))]  ""  "{  operands[2] = negate_rtx (SImode, operands[2]);}");; logical shift instructions(define_insn "lshlsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(lshift:SI (match_operand:SI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "rmn")))]  ""  "lshd %2,%0")(define_insn "lshlhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(lshift:HI (match_operand:HI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "rmn")))]  ""  "lshw %2,%0")(define_insn "lshlqi3"  [(set (match_operand:QI 0 "general_operand" "=g")	(lshift:QI (match_operand:QI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "rmn")))]  ""  "lshb %2,%0");; Logical right shift on the 32k works by negating the shift count.(define_expand "lshrsi3"  [(set (match_operand:SI 0 "general_operand" "=g")	(lshift:SI (match_operand:SI 1 "general_operand" "g")		   (match_operand:SI 2 "general_operand" "g")))]  ""  "{  operands[2] = negate_rtx (SImode, operands[2]);}")(define_expand "lshrhi3"  [(set (match_operand:HI 0 "general_operand" "=g")	(lshift:HI (match_operand:HI 1 "general_operand" "g")		   (match_operand:SI 2 "general_operand" "g")))]  ""