;;- Machine description for GNU compiler;;- Convex Version;;   Copyright (C) 1989 Free Software Foundation, Inc.;; This file is part of GNU CC.;; GNU CC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 1, or (at your option);; any later version.;; GNU CC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GNU CC; see the file COPYING.  If not, write to;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.;;- Instruction patterns.  When multiple patterns apply,;;- the first one in the file is chosen.;;-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.;;-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code;;- updates for most instructions.;; Put tstsi first among test insns so it matches a CONST_INT operand.(define_insn "tstsi"  [(set (cc0)	(match_operand:SI 0 "register_operand" "r"))]  ""  "* return set_cmp (operands[0], const0_rtx, 'w');")(define_insn "tsthi"  [(set (cc0)	(match_operand:HI 0 "register_operand" "r"))]  ""  "* return set_cmp (operands[0], const0_rtx, 'h');")(define_expand "tstqi"  [(set (match_dup 1)	(sign_extend:SI (match_operand:QI 0 "register_operand" "r")))   (set (cc0)	(match_dup 1))]  ""  "operands[1] = gen_reg_rtx (SImode);")(define_insn "tstdi"  [(set (cc0)	(match_operand:DI 0 "register_operand" "d"))   (clobber (reg:DI 1))]  ""  "*{  output_asm_insn (\"ld.l #0,s1\");  return set_cmp (operands[0], gen_rtx (REG, DImode, 1), 'l');}")(define_expand "tstdf"  [(set (cc0)	(compare (match_operand:DF 0 "register_operand" "d")		 (match_dup 1)))]  ""  "operands[1] = force_reg (DFmode, dconst0_rtx);")(define_insn "tstsf"  [(set (cc0)	(match_operand:SF 0 "register_operand" "d"))]  ""  "* return set_cmp (operands[0], fconst0_rtx, 's');");; Put cmpsi first among compare insns so it matches two CONST_INT operands.(define_insn "cmpsi"  [(set (cc0)	(compare (match_operand:SI 0 "nonmemory_operand" "d,a,i,r")		 (match_operand:SI 1 "nonmemory_operand" "d,a,r,i")))]  ""  "* return set_cmp (operands[0], operands[1], 'w');")(define_insn "cmphi"  [(set (cc0)	(compare (match_operand:HI 0 "nonmemory_operand" "d,a,r,i")		 (match_operand:HI 1 "nonmemory_operand" "d,a,i,r")))]  ""  "* return set_cmp (operands[0], operands[1], 'h');")(define_insn ""  [(set (cc0)	(compare (sign_extend:SI (match_operand:QI 0 "register_operand" "d"))		 (sign_extend:SI (match_operand:QI 1 "register_operand" "d"))))]  ""  "* return set_cmp (operands[0], operands[1], 'b');")(define_insn "cmpdi"  [(set (cc0)	(compare (match_operand:DI 0 "register_operand" "d")		 (match_operand:DI 1 "register_operand" "d")))]  ""  "* return set_cmp (operands[0], operands[1], 'l');")(define_insn "cmpdf"  [(set (cc0)	(compare (match_operand:DF 0 "register_operand" "d")		 (match_operand:DF 1 "register_operand" "d")))]  ""  "* return set_cmp (operands[0], operands[1], 'd');")(define_insn "cmpsf"  [(set (cc0)	(compare (match_operand:SF 0 "nonmemory_operand" "dF,d")		 (match_operand:SF 1 "nonmemory_operand" "d,F")))]  ""  "* return set_cmp (operands[0], operands[1], 's');")(define_insn "movdf"  [(set (match_operand:DF 0 "general_operand" "=g,d")	(match_operand:DF 1 "general_operand" "d,gG"))]  ""  "*{  if (push_operand (operands[0], DFmode))    return \"psh.l %1\";  else if (GET_CODE (operands[0]) == MEM)    return \"st.l %1,%0\";  else if (GET_CODE (operands[1]) == REG)    return \"mov %1,%0\";  else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))    {      operands[1] = gen_rtx (CONST_INT, VOIDmode,			     const_double_high_int (operands[1]));      return \"ld.d %1,%0\";    }  else    return \"ld.l %1,%0\";}")(define_insn "movsf"  [(set (match_operand:SF 0 "general_operand" "=g,d")	(match_operand:SF 1 "general_operand" "d,gF"))]  ""  "*{  if (push_operand (operands[0], SFmode))    return \"psh.w %1\";  else if (GET_CODE (operands[0]) == MEM)    return \"st.s %1,%0\";  else if (GET_CODE (operands[1]) == REG)    return \"mov.s %1,%0\";  else    return \"ld.s %1,%0\";}")(define_insn "movdi"  [(set (match_operand:DI 0 "general_operand" "=g,d")	(match_operand:DI 1 "general_operand" "d,gG"))]  ""  "*{  if (push_operand (operands[0], DImode))    return \"psh.l %1\";  else if (GET_CODE (operands[0]) == MEM)    return \"st.l %1,%0\";  else if (GET_CODE (operands[1]) == REG)    return \"mov %1,%0\";  else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))    {      operands[1] = gen_rtx (CONST_INT, VOIDmode,			     const_double_high_int (operands[1]));      return \"ld.d %1,%0\";    }  else    return \"ld.l %1,%0\";}");; Special case of movsi, needed to express A-reg preference.(define_insn ""  [(set (match_operand:SI 0 "push_operand" "=<")	(plus:SI (match_operand:SI 1 "register_operand" "a")		 (match_operand:SI 2 "immediate_operand" "i")))]  "operands[1] != stack_pointer_rtx"  "pshea %a2(%1)")(define_insn "movsi"  [(set (match_operand:SI 0 "general_operand" "=g,r,<")	(match_operand:SI 1 "general_operand" "r,g,io"))]  ""  "*{   if (push_operand (operands[0], SImode))    {      if (GET_CODE (operands[1]) == REG)	return \"psh.w %1\";      else        return \"pshea %a1\";    }  if (GET_CODE (operands[0]) == MEM)    return \"st.w %1,%0\";  if (GET_CODE (operands[1]) != REG)    return \"ld.w %1,%0\";  if (S_REG_P (operands[0]) && S_REG_P (operands[1]))    return \"mov.w %1,%0\";  return \"mov %1,%0\";}")(define_insn "movhi"  [(set (match_operand:HI 0 "general_operand" "=g,r")	(match_operand:HI 1 "general_operand" "r,g"))]  ""  "*{  if (push_operand (operands[0], HImode))    abort ();  else if (GET_CODE (operands[0]) == MEM)    return \"st.h %1,%0\";  else if (GET_CODE (operands[1]) == REG)     {      if (S_REG_P (operands[0]) && S_REG_P (operands[1]))	return \"mov.w %1,%0\";      else        return \"mov %1,%0\";    }  else if (GET_CODE (operands[1]) == CONST_INT)    return \"ld.w %1,%0\";  else    return \"ld.h %1,%0\";}")(define_insn "movqi"  [(set (match_operand:QI 0 "general_operand" "=g,r")	(match_operand:QI 1 "general_operand" "r,g"))]  ""  "*{  if (push_operand (operands[0], QImode))    abort ();  else if (GET_CODE (operands[0]) == MEM)    return \"st.b %1,%0\";  else if (GET_CODE (operands[1]) == REG)    {      if (S_REG_P (operands[0]) && S_REG_P (operands[1]))	return \"mov.w %1,%0\";      else        return \"mov %1,%0\";    }  else if (GET_CODE (operands[1]) == CONST_INT)    return \"ld.w %1,%0\";  else    return \"ld.b %1,%0\";}");; Extension and truncation insns.;; Those for integer source operand;; are ordered widest source type first.(define_insn "truncsiqi2"  [(set (match_operand:QI 0 "register_operand" "=d,a")	(truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]  ""  "cvtw.b %1,%0")(define_insn "truncsihi2"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]  ""  "cvtw.h %1,%0")(define_insn "trunchiqi2"  [(set (match_operand:QI 0 "register_operand" "=r")	(truncate:QI (match_operand:HI 1 "register_operand" "0")))]  ""  "")(define_insn "truncdisi2"  [(set (match_operand:SI 0 "register_operand" "=d")	(truncate:SI (match_operand:DI 1 "register_operand" "d")))]  ""  "cvtl.w %1,%0")(define_insn "extendsidi2"  [(set (match_operand:DI 0 "register_operand" "=d")	(sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]  ""  "cvtw.l %1,%0")(define_insn "extendhisi2"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]  ""  "cvth.w %1,%0")(define_insn "extendqihi2"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]  ""  "cvtb.w %1,%0")(define_insn "extendqisi2"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]  ""  "cvtb.w %1,%0")(define_insn "extendsfdf2"  [(set (match_operand:DF 0 "register_operand" "=d")	(float_extend:DF (match_operand:SF 1 "register_operand" "d")))]  ""  "cvts.d %1,%0")(define_insn "truncdfsf2"  [(set (match_operand:SF 0 "register_operand" "=d")	(float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]  ""  "cvtd.s %1,%0")(define_insn "zero_extendhisi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]  ""  "and #0xffff,%0")(define_insn "zero_extendqihi2"  [(set (match_operand:HI 0 "register_operand" "=r")	(zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]  ""  "and #0xff,%0")(define_insn "zero_extendqisi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]  ""  "and #0xff,%0")(define_insn "zero_extendsidi2"  [(set (match_operand:DI 0 "register_operand" "=d")	(zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]  ""  "ld.u #0,%0");; Fix-to-float conversion insns.;; Note that the ones that start with SImode come first.;; That is so that an operand that is a CONST_INT;; (and therefore lacks a specific machine mode).;; will be recognized as SImode (which is always valid);; rather than as QImode or HImode.(define_insn "floatsisf2"  [(set (match_operand:SF 0 "register_operand" "=d")	(float:SF (match_operand:SI 1 "register_operand" "d")))]  ""  "cvtw.s %1,%0")(define_insn "floatdisf2"  [(set (match_operand:SF 0 "register_operand" "=d")	(float:SF (match_operand:DI 1 "register_operand" "d")))]  ""  "cvtl.s %1,%0")(define_insn "floatsidf2"  [(set (match_operand:DF 0 "register_operand" "=d")	(float:DF (match_operand:SI 1 "register_operand" "d")))]  "TARGET_C2"  "cvtw.d %1,%0")(define_insn "floatdidf2"  [(set (match_operand:DF 0 "register_operand" "=d")	(float:DF (match_operand:DI 1 "register_operand" "d")))]  ""  "cvtl.d %1,%0");; Float-to-fix conversion insns.(define_insn "fix_truncsfsi2"  [(set (match_operand:SI 0 "register_operand" "=d")	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]  ""  "cvts.w %1,%0")(define_insn "fix_truncsfdi2"  [(set (match_operand:DI 0 "register_operand" "=d")	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]  ""  "cvts.l %1,%0")(define_insn "fix_truncdfsi2"  [(set (match_operand:SI 0 "register_operand" "=d")	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]  ""  "*{  if (TARGET_C2)    return \"cvtd.w %1,%0\";  return \"cvtd.l %1,%0\";}")(define_insn "fix_truncdfdi2"  [(set (match_operand:DI 0 "register_operand" "=d")	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]  ""  "cvtd.l %1,%0");;- All kinds of add instructions.(define_insn "adddf3"  [(set (match_operand:DF 0 "register_operand" "=d")	(plus:DF (match_operand:DF 1 "register_operand" "%0")		 (match_operand:DF 2 "register_operand" "d")))]  ""  "add.d %2,%0")(define_insn "addsf3"  [(set (match_operand:SF 0 "register_operand" "=d")	(plus:SF (match_operand:SF 1 "register_operand" "%0")		 (match_operand:SF 2 "nonmemory_operand" "dF")))]  ""  "add.s %2,%0")(define_insn "adddi3"