[(set (match_operand:DI 0 "register_operand" "=d")	(plus:DI (match_operand:DI 1 "register_operand" "%0")		 (match_operand:DI 2 "register_operand" "d")))]  ""  "add.l %2,%0");; special case of addsi3, needed to specify an A reg for the destination ;; when the source is a sum involving FP or AP.(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=a")	(plus:SI (match_operand:SI 1 "register_operand" "%a")		 (match_operand:SI 2 "immediate_operand" "i")))]  "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx"  "ldea %a2(%1),%0")(define_insn "addsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a,a")	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%0,0,a")		 (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]  ""  "* switch (which_alternative) { case 0: case 1:    return \"add.w %2,%0\"; case 2:   if ((TARGET_C2 || A_REG_P (operands[0]))       && operands[1] != stack_pointer_rtx)     return \"ldea %a2(%1),%0\";   else     return \"mov %1,%0\;add.w %2,%0\";}")(define_insn "addhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(plus:HI (match_operand:HI 1 "register_operand" "%0,0")		 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "add.h %2,%0")(define_insn "addqi3"  [(set (match_operand:QI 0 "register_operand" "=d")	(plus:QI (match_operand:QI 1 "register_operand" "%0")		 (match_operand:QI 2 "register_operand" "d")))]  ""  "add.b %2,%0");;- All kinds of subtract instructions.(define_insn "subdf3"  [(set (match_operand:DF 0 "register_operand" "=d")	(minus:DF (match_operand:DF 1 "register_operand" "0")		  (match_operand:DF 2 "register_operand" "d")))]  ""  "sub.d %2,%0")(define_insn "subsf3"  [(set (match_operand:SF 0 "register_operand" "=d")	(minus:SF (match_operand:SF 1 "register_operand" "0")		  (match_operand:SF 2 "nonmemory_operand" "dF")))]  ""  "sub.s %2,%0")(define_insn "subdi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(minus:DI (match_operand:DI 1 "register_operand" "0")		  (match_operand:DI 2 "register_operand" "d")))]  ""  "sub.l %2,%0")(define_insn "subsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(minus:SI (match_operand:SI 1 "register_operand" "0,0")		  (match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "sub.w %2,%0")(define_insn "subhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(minus:HI (match_operand:HI 1 "register_operand" "0,0")		  (match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "sub.h %2,%0")(define_insn "subqi3"  [(set (match_operand:QI 0 "register_operand" "=d")	(minus:QI (match_operand:QI 1 "register_operand" "0")		  (match_operand:QI 2 "register_operand" "d")))]  ""  "sub.b %2,%0");;- Multiply instructions.(define_insn "muldf3"  [(set (match_operand:DF 0 "register_operand" "=d")	(mult:DF (match_operand:DF 1 "register_operand" "%0")		 (match_operand:DF 2 "register_operand" "d")))]  ""  "mul.d %2,%0")(define_insn "mulsf3"  [(set (match_operand:SF 0 "register_operand" "=d")	(mult:SF (match_operand:SF 1 "register_operand" "%0")		 (match_operand:SF 2 "nonmemory_operand" "dF")))]  ""  "mul.s %2,%0")(define_insn "muldi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(mult:DI (match_operand:DI 1 "register_operand" "%0")		 (match_operand:DI 2 "register_operand" "d")))]  ""  "mul.l %2,%0")(define_insn "mulsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(mult:SI (match_operand:SI 1 "register_operand" "%0,0")		 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "mul.w %2,%0")(define_insn "mulhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(mult:HI (match_operand:HI 1 "register_operand" "%0,0")		 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "mul.h %2,%0")(define_insn "mulqi3"  [(set (match_operand:QI 0 "register_operand" "=d")	(mult:QI (match_operand:QI 1 "register_operand" "%0")		 (match_operand:QI 2 "register_operand" "d")))]  ""  "mul.b %2,%0");;- Divide instructions.(define_insn "divdf3"  [(set (match_operand:DF 0 "register_operand" "=d")	(div:DF (match_operand:DF 1 "register_operand" "0")		(match_operand:DF 2 "register_operand" "d")))]  ""  "div.d %2,%0")(define_insn "divsf3"  [(set (match_operand:SF 0 "register_operand" "=d")	(div:SF (match_operand:SF 1 "register_operand" "0")		(match_operand:SF 2 "nonmemory_operand" "dF")))]  ""  "div.s %2,%0")(define_insn "divdi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(div:DI (match_operand:DI 1 "register_operand" "0")		(match_operand:DI 2 "register_operand" "d")))]  ""  "div.l %2,%0")(define_insn "udivdi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(udiv:DI (match_operand:DI 1 "register_operand" "d")		 (match_operand:DI 2 "register_operand" "d")))]  ""  "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp")(define_insn "divsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(div:SI (match_operand:SI 1 "register_operand" "0,0")		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "div.w %2,%0")(define_insn "divhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(div:HI (match_operand:HI 1 "register_operand" "0,0")		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "div.h %2,%0")(define_insn "divqi3"  [(set (match_operand:QI 0 "register_operand" "=d")	(div:QI (match_operand:QI 1 "register_operand" "0")		(match_operand:QI 2 "register_operand" "d")))]  ""  "div.b %2,%0");; - and, or, xor(define_insn "anddi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(and:DI (match_operand:DI 1 "register_operand" "%0")		(match_operand:DI 2 "register_operand" "d")))]  ""  "and %2,%0")(define_insn "andsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(and:SI (match_operand:SI 1 "register_operand" "%0,0")		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "and %2,%0")(define_insn "andhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(and:HI (match_operand:HI 1 "register_operand" "%0,0")		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "and %2,%0")(define_insn "andqi3"  [(set (match_operand:QI 0 "register_operand" "=d,a")	(and:QI (match_operand:QI 1 "register_operand" "%0,0")		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]  ""  "and %2,%0");;- Bit set instructions.(define_insn "iordi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(ior:DI (match_operand:DI 1 "register_operand" "%0")		(match_operand:DI 2 "register_operand" "d")))]  ""  "or %2,%0")(define_insn "iorsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "or %2,%0")(define_insn "iorhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(ior:HI (match_operand:HI 1 "register_operand" "%0,0")		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "or %2,%0")(define_insn "iorqi3"  [(set (match_operand:QI 0 "register_operand" "=d,a")	(ior:QI (match_operand:QI 1 "register_operand" "%0,0")		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]  ""  "or %2,%0");;- xor instructions.(define_insn "xordi3"  [(set (match_operand:DI 0 "register_operand" "=d")	(xor:DI (match_operand:DI 1 "register_operand" "%0")		(match_operand:DI 2 "register_operand" "d")))]  ""  "xor %2,%0")(define_insn "xorsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "xor %2,%0")(define_insn "xorhi3"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(xor:HI (match_operand:HI 1 "register_operand" "%0,0")		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]  ""  "xor %2,%0")(define_insn "xorqi3"  [(set (match_operand:QI 0 "register_operand" "=d,a")	(xor:QI (match_operand:QI 1 "register_operand" "%0,0")		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]  ""  "xor %2,%0")(define_insn "negdf2"  [(set (match_operand:DF 0 "register_operand" "=d")	(neg:DF (match_operand:DF 1 "register_operand" "d")))]  ""  "neg.d %1,%0")(define_insn "negsf2"  [(set (match_operand:SF 0 "register_operand" "=d")	(neg:SF (match_operand:SF 1 "register_operand" "d")))]  ""  "neg.s %1,%0")(define_insn "negdi2"  [(set (match_operand:DI 0 "register_operand" "=d")	(neg:DI (match_operand:DI 1 "register_operand" "d")))]  ""  "neg.l %1,%0")(define_insn "negsi2"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(neg:SI (match_operand:SI 1 "register_operand" "d,a")))]  ""  "neg.w %1,%0")(define_insn "neghi2"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(neg:HI (match_operand:HI 1 "register_operand" "d,a")))]  ""  "neg.h %1,%0")(define_insn "negqi2"  [(set (match_operand:QI 0 "register_operand" "=d")	(neg:QI (match_operand:QI 1 "register_operand" "d")))]  ""  "neg.b %1,%0")(define_insn "one_cmpldi2"  [(set (match_operand:DI 0 "register_operand" "=d")	(not:DI (match_operand:DI 1 "register_operand" "d")))]  ""  "not %1,%0")(define_insn "one_cmplsi2"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(not:SI (match_operand:SI 1 "register_operand" "d,a")))]  ""  "not %1,%0")(define_insn "one_cmplhi2"  [(set (match_operand:HI 0 "register_operand" "=d,a")	(not:HI (match_operand:HI 1 "register_operand" "d,a")))]  ""  "not %1,%0")(define_insn "one_cmplqi2"  [(set (match_operand:QI 0 "register_operand" "=d,a")	(not:QI (match_operand:QI 1 "register_operand" "d,a")))]  ""  "not %1,%0");;- shifts;;;; Convex shift instructions are unsigned.;; To make signed right shifts:;; for SImode, sign extend to DImode and shift, works for 0..32;; for DImode, shift and then extend the sign, works for 0..63;;;; It is very sad that DImode right shift 64 fails, but I don't see;; any reasonable way to handle it.  ANSI only requires up to 63.(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(ashift:SI (match_operand:SI 1 "register_operand" "0")		   (match_operand:SI 2 "immediate_operand" "i")))]  "INTVAL (operands[2]) >= 0"  "*{  if (operands[2] == const1_rtx)    return \"add.w %0,%0\";  else if (TARGET_C2 && S_REG_P (operands[0]))    return \"shf.w %2,%0\";  else    return \"shf %2,%0\";}")(define_insn "ashlsi3"  [(set (match_operand:SI 0 "register_operand" "=d")	(ashift:SI (match_operand:SI 1 "register_operand" "0")		   (match_operand:SI 2 "nonmemory_operand" "di")))]  ""  "*{  if (operands[2] == const1_rtx)    return \"add.w %0,%0\";  else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)    return TARGET_C2 ? \"shf.w %2,%0\" : \"shf %2,%0\";  else    return \"cvtw.l %0,%0\;shf %2,%0\";}")(define_expand "ashrsi3"  [(set (match_operand:SI 0 "register_operand" "=d")	(ashift:SI (match_operand:SI 1 "register_operand" "0")		   (match_operand:SI 2 "nonmemory_operand" "di")))]  ""  "operands[2] = negate_rtx (SImode, operands[2]);")(define_insn "lshlsi3"  [(set (match_operand:SI 0 "register_operand" "=d,a")	(lshift:SI (match_operand:SI 1 "register_operand" "0,0")		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]  ""  "*{  if (operands[2] == const1_rtx)    return \"add.w %0,%0\";  if (S_REG_P (operands[0]))    {      if (TARGET_C2)	return \"shf.w %2,%0\";      else if (GET_CODE (operands[2]) == CONST_INT	       && INTVAL (operands[2]) >= 0)        return \"shf %2,%0\";      else        return \"ld.u #0,%0\;shf %2,%0\";    }  return \"shf %2,%0\";}")(define_expand "lshrsi3"  [(set (match_operand:SI 0 "register_operand" "=d")	(lshift:SI (match_operand:SI 1 "register_operand" "0")		   (match_operand:SI 2 "nonmemory_operand" "di")))]  ""  "operands[2] = negate_rtx (SImode, operands[2]);");; signed  a >> b  is;;     ((a >> b) ^ signbit) - signbit;; where signbit is (1 << 63) >> b(define_expand "ashldi3"  [(match_operand:DI 0 "register_operand" "=d")   (match_operand:DI 1 "register_operand" "0")   (match_operand:SI 2 "nonmemory_operand" "di")   (match_dup 3)]  ""