output_asm_insn (\"bc1t\\t%2\\t\\t# bltu\", br_ops);    }  else    {      output_asm_insn (\"bltu\\t%0,%1,%2\\t\\t# bltu\", br_ops);    }  return \"\";}")(define_insn "bge"  [(set (pc)	(if_then_else (ge (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# bge\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bge\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# bge\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bge\", br_ops);    }  else    {      output_asm_insn (\"bge\\t%0,%1,%2\\t\\t# bge\", br_ops);    }  return \"\";}")(define_insn "bgeu"  [(set (pc)	(if_then_else (geu (cc0)			   (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# bgeu\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bgeu\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# bgeu\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bgeu\", br_ops);    }  else    {      output_asm_insn (\"bgeu\\t%0,%1,%2\\t\\t# bgeu\", br_ops);    }  return \"\";}")(define_insn "ble"  [(set (pc)	(if_then_else (le (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# ble\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# ble\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# ble\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# ble\", br_ops);    }  else    {      output_asm_insn (\"ble\\t%0,%1,%2\\t\\t# ble\", br_ops);    }  return \"\";}")(define_insn "bleu"  [(set (pc)	(if_then_else (leu (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# ble\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# ble\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# ble\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# ble\", br_ops);    }  else    {      output_asm_insn (\"bleu\\t%0,%1,%2\\t\\t# bleu\", br_ops);    }  return \" #\\tbleu\\t%l0\\t\\t# bleu\";}")(define_insn ""  [(set (pc)	(if_then_else (ne (cc0)			  (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.eq.d\\t%0,%1\\t\\t# beq\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# beq\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.eq.s\\t%0,%1\\t\\t# beq\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# beq\", br_ops);    }  else    {      output_asm_insn (\"beq\\t%0,%1,%2\\t\\t# beq Inv.\", br_ops);    }  return \"\";}")(define_insn ""  [(set (pc)	(if_then_else (eq (cc0)			  (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.eq.d\\t%0,%1\\t\\t# bne\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bne\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.eq.s\\t%0,%1\\t\\t# bne\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# beq\", br_ops);    }  else    {      output_asm_insn (\"bne\\t%0,%1,%2\\t\\t# bne Inv.\", br_ops);    }  return \"\";}")(define_insn ""  [(set (pc)	(if_then_else (le (cc0)			  (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# bgt\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# beq\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# bgt\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# beq\", br_ops);    }  else    {      output_asm_insn (\"bgt\\t%0,%1,%2\\t\\t# bgt Inv.\", br_ops);    }  return \"\";}")(define_insn ""  [(set (pc)	(if_then_else (leu (cc0)			   (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# bgt\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# beq\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# bgt\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# beq\", br_ops);    }  else    {      output_asm_insn (\"bgtu\\t%0,%1,%2\\t\\t# bgtu Inv.\", br_ops);    }  return \" #\\tbgtu\\t%l0\\t\\t# bgtu\";}")(define_insn ""  [(set (pc)	(if_then_else (ge (cc0)			  (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# blt\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# beq\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# blt\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# beq\", br_ops);    }  else    {      output_asm_insn (\"blt\\t%0,%1,%2\\t\\t# blt Inv.\", br_ops);    }  return \"\";}")(define_insn ""  [(set (pc)	(if_then_else (geu (cc0)			   (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# bltu\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# bltu\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# bltu\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# bltu\", br_ops);    }  else    {      output_asm_insn (\"bltu\\t%0,%1,%2\\t\\t# bltu Inv.\", br_ops);    }  return \" #\\tbltu\\t%l0\\t\\t# bltu\";}")(define_insn ""  [(set (pc)	(if_then_else (lt (cc0)			  (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# bge\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bge (DF) Inv.\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# bge\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bge (SF) Inv.\", br_ops);    }  else    {      output_asm_insn (\"bge\\t%0,%1,%2\\t\\t# bge Inv.\", br_ops);    }  return \"\";}")(define_insn ""  [(set (pc)	(if_then_else (ltu (cc0)			   (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# bge\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bgeu (DF)  Inv.\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# bge\", br_ops);      output_asm_insn (\"bc1f\\t%2\\t\\t# bgeu (SF )Inv.\", br_ops);    }  else    {      output_asm_insn (\"bgeu\\t%0,%1,%2\\t\\t# bgeu Inv.\", br_ops);    }  return \" #\\tbgeu\\t%l0\\t\\t# bgeu\";}")(define_insn ""  [(set (pc)	(if_then_else (gt (cc0)			  (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# ble\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# ble\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# ble\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# ble\", br_ops);    }  else    {      output_asm_insn (\"ble\\t%0,%1,%2\\t\\t# ble Inv.\", br_ops);    }  return \"\";}")(define_insn ""  [(set (pc)	(if_then_else (gtu (cc0)			   (const_int 0))		      (pc)		      (label_ref (match_operand 0 "" ""))))]  ""  "*{  rtx br_ops[3];  enum machine_mode mode;  compare_restore (br_ops,  &mode, insn);  br_ops[2] = operands[0];  if (mode == DFmode)    {      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# bleu\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# bleu\", br_ops);    }  else if  (mode == SFmode)    {      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# bleu\", br_ops);      output_asm_insn (\"bc1t\\t%2\\t\\t# bleu\", br_ops);    }  else    {      output_asm_insn (\"bleu\\t%0,%1,%2\\t\\t# bleu Inv.\", br_ops);    }  return \"\";}");;;;  ....................;;;;          LINKAGE;;;;  ....................(define_insn "call"  [(call (match_operand 0 "memory_operand" "m")	 (match_operand 1 "" "i"))   (clobber (reg:SI 31))]  ""  "*{  register rtx target = XEXP (operands[0], 0);  if (GET_CODE (target) == SYMBOL_REF)    return \"jal\\t%0\";  else    {      operands[0] = target;      return \"jal\\t$31,%0\";    }}")(define_insn "call_value"  [(set (match_operand 0 "" "=rf")        (call (match_operand 1 "memory_operand" "m")              (match_operand 2 "" "i")))   (clobber (reg:SI 31))]  ""  "*{  register rtx target = XEXP (operands[1], 0);  if (GET_CODE (target) == SYMBOL_REF)    return \"jal\\t%1\";  else    {      operands[1] = target;      return \"jal\\t$31,%1\";    }}")(define_insn "nop"  [(const_int 0)]  ""  ".set\\tnoreorder\;nop\;.set\\treorder")(define_insn "probe"  [(mem:SI (reg:SI 29))]  ""  "*{  operands[0] = gen_rtx (REG, SImode, 1);  operands[1] = stack_pointer_rtx;  return \".set\\tnoat\;lw\\t%0,0(%1)\\t\\t# stack probe\;.set\\tat\";}");;;;- Local variables:;;- mode:emacs-lisp;;- comment-start: ";;- ";;- eval: (set-syntax-table (copy-sequence (syntax-table)));;- eval: (modify-syntax-entry ?[ "(]");;- eval: (modify-syntax-entry ?] ")[");;- eval: (modify-syntax-entry ?{ "(}");;- eval: (modify-syntax-entry ?} "){");;- End: