/* Definitions of target machine for GNU compiler.  Convex version.   Copyright (C) 1989, 1990 Free Software Foundation, Inc.This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 1, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING.  If not, write tothe Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  *//* Use the proper incantation to search Posix-compliant libraries. */#define LINK_SPEC \"%{!traditional:-Eposix}%{traditional:-Enoposix}\ -A__iob=___ap$iob\ -A_use_libc_sema=___ap$use_libc_sema\ -L /usr/lib"/* Use the matching startup files. */#define STARTFILE_SPEC \"%{pg:/usr/lib/crt/gcrt0.o}\%{!pg:%{p:/usr/lib/crt/mcrt0.o}\%{!p:/usr/lib/crt/crt0.o}}"/* Names to predefine in the preprocessor for this target machine.  */#define CPP_PREDEFINES "-Dconvex -Dunix"/* Print subsidiary information on the compiler version in use.  */#define TARGET_VERSION fprintf (stderr, " (convex)");/* Run-time compilation parameters selecting different hardware subsets.  */extern int target_flags;/* Macros used in the machine description to test the flags.  *//*    -mc1		avoid C2-only instructions; default on C1 host   -mc2		use C2-only instructions; default on C2 host   -margcount	use standard calling sequence, with arg count word   -mnoargcount don't push arg count (it's in the symbol table) (usually)*/#define TARGET_C1 (target_flags & 1)#define TARGET_C2 (target_flags & 2)#define TARGET_ARGCOUNT (target_flags & 4)/* Macro to define tables used to set the flags.   This is a list in braces of pairs in braces,   each pair being { "NAME", VALUE }   where VALUE is the bits to set or minus the bits to clear.   An empty string NAME is used to identify the default VALUE.  */#define TARGET_SWITCHES \  { { "c1", 1 }, 	\    { "c2", 2 },	\    { "noc1", -1 }, 	\    { "noc2", -2 },	\    { "argcount", 4 },  \    { "noargcount", -4 }, \    { "", TARGET_DEFAULT }}/* Default target_flags if no switches specified.  */#ifndef TARGET_DEFAULT#define TARGET_DEFAULT 0#endif/* Allow $ in identifiers */#define DOLLARS_IN_IDENTIFIERS 1/* Definitions for g++.  *//* Do not put out GNU stabs for constructors and destructors.   ld does not like them.  */#define FASCIST_ASSEMBLER/* Convex has negative addresses, so use positive numbers   to mean `vtable index'.  */#define VTABLE_USES_MASK#define VINDEX_MAX ((unsigned) 0x80000000)/* Target machine storage layout *//* Define this if most significant bit is lowest numbered   in instructions that operate on numbered bit-fields. */#define BITS_BIG_ENDIAN/* Define this if most significant byte of a word is the lowest numbered.  */#define BYTES_BIG_ENDIAN/* Define this if most significant word of a multiword number is numbered.  *//* Lie, so that gcc will take the low part of double reg N in reg N.  *//* #define WORDS_BIG_ENDIAN *//* Number of bits in an addressible storage unit */#define BITS_PER_UNIT 8/* Width in bits of a "word", which is the contents of a machine register.   Note that this is not necessarily the width of data type `int';   if using 16-bit ints on a 68000, this would still be 32.   But on a machine with 16-bit registers, this would be 16.  */#define BITS_PER_WORD 32/* Width of a word, in units (bytes).  */#define UNITS_PER_WORD 4/* Width in bits of a pointer.   See also the macro `Pmode' defined below.  */#define POINTER_SIZE 32/* Allocation boundary (in *bits*) for storing pointers in memory.  */#define POINTER_BOUNDARY 32/* Allocation boundary (in *bits*) for storing arguments in argument list.  */#define PARM_BOUNDARY 32/* Boundary (in *bits*) on which stack pointer should be aligned.  */#define STACK_BOUNDARY 32/* Allocation boundary (in *bits*) for the code of a function.  */#define FUNCTION_BOUNDARY 16/* Alignment of field after `int : 0' in a structure.  */#define EMPTY_FIELD_BOUNDARY 32/* Every structure's size must be a multiple of this.  */#define STRUCTURE_SIZE_BOUNDARY 8/* A bitfield declared as `int' forces `int' alignment for the struct.  */#define PCC_BITFIELD_TYPE_MATTERS 1/* No data type wants to be aligned rounder than this.  *//* beware of doubles in structs -- 64 is incompatible with pcc */#define BIGGEST_ALIGNMENT 32/* Define this if move instructions will actually fail to work   when given unaligned data.  *//* #define STRICT_ALIGNMENT *//* Standard register usage.  *//* Number of actual hardware registers.   The hardware registers are assigned numbers for the compiler   from 0 to just below FIRST_PSEUDO_REGISTER.   All registers that the compiler knows about must be given numbers,   even those that are not normally considered general registers.  */#define FIRST_PSEUDO_REGISTER 16/* 1 for registers that have pervasive standard uses   and are not available for the register allocator.   For Convex, these are AP, FP, and SP.  */#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1} /* 1 for registers not available across function calls.   These must include the FIXED_REGISTERS and also any   registers that can be used without being saved.   The latter must include the registers where values are returned   and the register where structure-value addresses are passed.   Aside from that, you can include as many other registers as you like.  */#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}/* Return number of consecutive hard regs needed starting at reg REGNO   to hold something of mode MODE.   This is ordinarily the length in words of a value of mode MODE   but can be less for certain modes in special long registers.   On Convex, all values fit in one register.  */#define HARD_REGNO_NREGS(REGNO, MODE)   1/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.   On Convex, S registers can hold any type, A registers can any nonfloat */#define HARD_REGNO_MODE_OK(REGNO, MODE) \  ((REGNO) < 8 || ((MODE) != SFmode && (MODE) != DFmode && (MODE) != DImode))/* Value is 1 if it is a good idea to tie two pseudo registers   when one has mode MODE1 and one has mode MODE2.   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,   for any hard reg, then this must be 0 for correct output.  */#define MODES_TIEABLE_P(MODE1, MODE2)  \    (((MODE1) == SFmode || (MODE1) == DFmode || (MODE1) == DImode) \     == ((MODE2) == SFmode || (MODE2) == DFmode || (MODE2) == DImode))/* Specify the registers used for certain standard purposes.   The values of these macros are register numbers.  *//* Register to use for pushing function arguments.  */#define STACK_POINTER_REGNUM 8/* Base register for access to local variables of the function.  */#define FRAME_POINTER_REGNUM 15/* Value should be nonzero if functions must have frame pointers.   Zero means the frame pointer need not be set up (and parms   may be accessed via the stack pointer) in functions that seem suitable.   This is computed in `reload', in reload1.c.  */#define FRAME_POINTER_REQUIRED 1/* Base register for access to arguments of the function.  */#define ARG_POINTER_REGNUM 14/* Register in which static-chain is passed to a function.  */#define STATIC_CHAIN_REGNUM 0/* Register in which address to store a structure value   is passed to a function.  */#define STRUCT_VALUE_REGNUM 9/* Define the classes of registers for register constraints in the   machine description.  Also define ranges of constants.   One of the classes must always be named ALL_REGS and include all hard regs.   If there is more than one class, another class must be named NO_REGS   and contain no registers.   The name GENERAL_REGS must be the name of a class (or an alias for   another name such as ALL_REGS).  This is the class of registers   that is allowed by "g" or "r" in a register constraint.   Also, registers outside this class are allocated only when   instructions express preferences for them.   The classes must be numbered in nondecreasing order; that is,   a larger-numbered class must never be contained completely   in a smaller-numbered class.   For any two classes, it is very desirable that there be another   class that represents their union.  */   /* Convex has classes A (address) and S (scalar).  Seems to work   better to put S first, here and in the md. */enum reg_class { NO_REGS, S_REGS, A_REGS, ALL_REGS, LIM_REG_CLASSES };#define N_REG_CLASSES (int) LIM_REG_CLASSES/* Since GENERAL_REGS is the same class as ALL_REGS,   don't give it a different class number; just make it an alias.  */#define GENERAL_REGS ALL_REGS/* Give names of register classes as strings for dump file.   */#define REG_CLASS_NAMES \ {"NO_REGS", "S_REGS", "A_REGS", "ALL_REGS" }/* Define which registers fit in which classes.   This is an initializer for a vector of HARD_REG_SET   of length N_REG_CLASSES.  */#define REG_CLASS_CONTENTS {0, 0x00ff, 0xff00, 0xffff}/* The same information, inverted:   Return the class number of the smallest class containing   reg number REGNO.  This could be a conditional expression   or could index an array.  */#define REGNO_REG_CLASS(REGNO) \  (S_REGNO_P (REGNO) ? S_REGS : A_REGS)#define S_REGNO_P(REGNO) ((REGNO) < 8)#define A_REGNO_P(REGNO) ((REGNO) >= 8)#define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))#define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))/* The class value for index registers, and the one for base regs.  */#define INDEX_REG_CLASS A_REGS#define BASE_REG_CLASS A_REGS/* Get reg_class from a letter such as appears in the machine description.  *//* S regs use the letter 'd' because 's' is taken. */#define REG_CLASS_FROM_LETTER(C) \  ((C) == 'a' ? A_REGS : (C) == 'd' ? S_REGS : NO_REGS)/* The letters I, J, K, L and M in a register constraint string   can be used to stand for particular ranges of immediate operands.   This macro defines what the ranges are.   C is the letter, and VALUE is a constant value.   Return 1 if VALUE is in the range specified by C.  *//* Convex uses only I:   32-bit value with sign bit off, usable as immediate in DImode logical      instructions and, or, xor */ #define CONST_OK_FOR_LETTER_P(VALUE, C)  ((VALUE) >= 0)/* Similar, but for floating constants, and defining letters G and H.   Here VALUE is the CONST_DOUBLE rtx itself.  *//* Convex uses only G:   value usable in ld.d (low word 0) or ld.l (high word all sign) */#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \  (LD_D_P (VALUE) || LD_L_P (VALUE))#define LD_D_P(X) (const_double_low_int (X) == 0)#define LD_L_P(X) (const_double_low_int (X) >= 0 \		   ? const_double_high_int (X) == 0 \		   : const_double_high_int (X) == -1)extern int const_double_low_int ();extern int const_double_high_int ();extern int const_double_float_int ();/* Given an rtx X being reloaded into a reg required to be   in class CLASS, return the class of reg to actually use.   In general this is just CLASS; but on some machines   in some cases it is preferable to use a more restrictive class.  */#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)/* Return the maximum number of consecutive registers   needed to represent mode MODE in a register of class CLASS.  */#define CLASS_MAX_NREGS(CLASS, MODE) 1/* Stack layout; function entry, exit and calling.  *//* Define this if pushing a word on the stack   makes the stack pointer a smaller address.  */#define STACK_GROWS_DOWNWARD/* Define this if the nominal address of the stack frame   is at the high-address end of the local variables;   that is, each additional local variable allocated   goes at a more negative offset in the frame.  */#define FRAME_GROWS_DOWNWARD/* Define this if should default to -fcaller-saves.  */