;}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(plus:SI (match_operand:SI 1 "general_operand" "0")		 (const_int 1)))]  ""  "inc%L0 %0")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(plus:SI (match_operand:SI 1 "general_operand" "0")		 (const_int -1)))]  ""  "dec%L0 %0")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(minus:SI (match_operand:SI 1 "general_operand" "0")		  (const_int 1)))]  ""  "dec%L0 %0")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")        (match_operand:QI 1 "address_operand" "p"))]  ""  "*{  CC_STATUS_INIT;  /* Adding a constant to a register is faster with an add.  */  if (GET_CODE (operands[1]) == PLUS      && GET_CODE (XEXP (operands[1], 1)) == CONST_INT      && rtx_equal_p (operands[0], XEXP (operands[1], 0)))    {      operands[1] = XEXP (operands[1], 1);      return AS2 (add%L0,%1,%0);    }  return \"lea%L0 %a1,%0\";}");;- conversion instructions;;- NONE;;- truncation instructions(define_insn "truncsiqi2"  [(set (match_operand:QI 0 "general_operand" "=q,m")	(truncate:QI	 (match_operand:SI 1 "general_operand" "qim,qn")))]  ""  "*{  if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)    return \"mov%L0 %1,%k0\";  return \"mov%B0 %b1,%0\";}")(define_insn "trunchiqi2"  [(set (match_operand:QI 0 "general_operand" "=q,m")	(truncate:QI	 (match_operand:HI 1 "general_operand" "qim,qn")))]  ""  "*{  if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)    return \"mov%W0 %1,%w0\";  return \"mov%B0 %b1,%0\";}")(define_insn "truncsihi2"  [(set (match_operand:HI 0 "general_operand" "=r,m")	(truncate:HI	 (match_operand:SI 1 "general_operand" "rim,rn")))]  ""  "*{  if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)    return \"mov%L0 %1,%k0\";  return \"mov%W0 %w1,%0\";}");;- zero extension instructions;; Note that the one starting from HImode comes before those for QImode;; so that a constant operand will match HImode, not QImode.(define_insn "zero_extendhisi2"  [(set (match_operand:SI 0 "general_operand" "=r")	(zero_extend:SI	 (match_operand:HI 1 "general_operand" "rm")))]  ""  "movz%W0%L0 %1,%0")(define_insn "zero_extendqihi2"  [(set (match_operand:HI 0 "general_operand" "=r")	(zero_extend:HI	 (match_operand:QI 1 "general_operand" "qm")))]  ""  "movz%B0%W0 %1,%0")(define_insn "zero_extendqisi2"  [(set (match_operand:SI 0 "general_operand" "=r")	(zero_extend:SI	 (match_operand:QI 1 "general_operand" "qm")))]  ""  "movz%B0%L0 %1,%0");;- sign extension instructions;; Note that the one starting from HImode comes before those for QImode;; so that a constant operand will match HImode, not QImode./*(define_insn "extendsidi2"  [(set (match_operand:DI 0 "general_operand" "=a")	(sign_extend:DI	 (match_operand:SI 1 "general_operand" "a")))]  ""  "clq")*/;; Note that the i386 programmers' manual says that the opcodes;; are named movsx..., but the assembler on Unix does not accept that.;; We use what the Unix assembler expects.(define_insn "extendhisi2"  [(set (match_operand:SI 0 "general_operand" "=r")	(sign_extend:SI	 (match_operand:HI 1 "general_operand" "rm")))]  ""  "movs%W0%L0 %1,%0")(define_insn "extendqihi2"  [(set (match_operand:HI 0 "general_operand" "=r")	(sign_extend:HI	 (match_operand:QI 1 "general_operand" "qm")))]  ""  "movs%B0%W0 %1,%0")(define_insn "extendqisi2"  [(set (match_operand:SI 0 "general_operand" "=r")	(sign_extend:SI	 (match_operand:QI 1 "general_operand" "qm")))]  "" "movs%B0%L0 %1,%0" );; Conversions between float and double.(define_insn "extendsfdf2"  [(set (match_operand:DF 0 "general_operand" "=fm,f,fm,fm")	(float_extend:DF	 (match_operand:SF 1 "general_operand" "m,0,f,!*r")))]  "TARGET_80387"  "*{  if (FP_REG_P (operands[0]))    {      output_movsf (operands[0], operands[1]);      RET;    }  if (FP_REG_P (operands[1]))    {      if (top_dead_p (insn))        fp_pop_df (operands[0]);      else        fp_store_df (operands[0]);      RET;    }  output_movsf (FP_TOP, operands[1]);  fp_pop_df (operands[0]);  RETCOM (extendsfdf2);}");; This cannot output into an f-reg because there is no way to be;; sure of truncating in that case.(define_insn "truncdfsf2"  [(set (match_operand:SF 0 "general_operand" "=m,!*r")	(float_truncate:SF	 (match_operand:DF 1 "general_operand" "f,f")))]  "TARGET_80387"  "*{  if (top_dead_p (insn))    fp_pop_sf (operands[0]);  else    fp_store_sf (operands[0]);  RETCOM (truncdfsf2);}");; Conversion between fixed point and floating point.;; Note that among the fix-to-float insns;; the ones that start with SImode come first.;; That is so that an operand that is a CONST_INT;; (and therefore lacks a specific machine mode).;; will be recognized as SImode (which is always valid);; rather than as QImode or HImode. The 80387 would not know;; what to do with the smaller sizes anyway. (I think).(define_insn "floatsisf2"  [(set (match_operand:SF 0 "general_operand" "=fm,fm")	(float:SF (match_operand:SI 1 "general_operand" "m,!*r")))]  "TARGET_80387"  "*{/*  fp_pop_level++; */  if (GET_CODE (operands[1]) != MEM)    {      rtx xops[2];      output_asm_insn (\"push%L0 %1\", operands);      operands[1] = AT_SP (SImode);      output_asm_insn (\"fild%L0 %1\", operands);      xops[0] = stack_pointer_rtx;      xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);      output_asm_insn (AS2 (add%L0,%1,%0), xops);    }  else    output_asm_insn (\"fild%L0 %1\", operands);  if (! FP_REG_P (operands[0]))    {/*      fp_pop_level--; */      return \"fstp%S0 %0\";    }  RET;}")(define_insn "floatsidf2"  [(set (match_operand:DF 0 "general_operand" "=fm,fm")	(float:DF (match_operand:SI 1 "general_operand" "m,!*r")))]  "TARGET_80387"  "*{/*  fp_pop_level++; */  if (GET_CODE (operands[1]) != MEM)    {      rtx xops[2];      output_asm_insn (\"push%L0 %1\", operands);      operands[1] = AT_SP (SImode);      output_asm_insn (\"fild%L0 %1\", operands);      xops[0] = stack_pointer_rtx;      xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);      output_asm_insn (AS2 (add%L0,%1,%0), xops);    }  else    output_asm_insn (\"fild%L0 %1\", operands);  if (! FP_REG_P (operands[0]))    {/*      fp_pop_level--; */      return \"fstp%Q0 %0\";    }  RET;}");; Convert a float to a float whose value is an integer.;; This is the first stage of converting it to an integer type.;; On the 387  truncating doub to an short integer shor can be performed:;	fstcw	-4(%esp)  ;save cw;	movw	-4(%esp),%ax;	orw	$0x0c00,%ax  ;set rounding to chop towards zero;	movw	%ax,-2(%esp) ;;	fldcw	-2(%esp)     ;;	fldl	doubl;	fistpl	-12(%esp)    ;store the round value;	fldcw	-4(%esp)     ;restore cw;	movl	-12(%esp),%eax;	movw	%ax,shor     ; move the result into shor.;; but it is probably better to have a call, rather than waste this;; space.  The last instruction would have been a movl if were;; going to an int instead of a short.;; For the moment we will go with the soft float for these./* These are incorrect since they don't set the rounding bits of CW flag.   The proper way to do that is to make the function prologue save the CW   and also construct the alternate CW value needed for these insns.   Then these insns can output two fldcw's, referring to fixed places in   the stack frame.;; Convert a float whose value is an integer;; to an actual integer.  Second stage of converting float to integer type.(define_insn "fix_truncsfqi2"  [(set (match_operand:QI 0 "general_operand" "=m,?*q")	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]  "TARGET_80387"  "*{  fp_pop_int (operands[0]);  RET;}")(define_insn "fix_truncsfhi2"  [(set (match_operand:HI 0 "general_operand" "=m,?*r")	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]  "TARGET_80387"  "*{  fp_pop_int (operands[0]);  RET;}")(define_insn "fix_truncsfsi2"  [(set (match_operand:SI 0 "general_operand" "=m,?*r")	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]  "TARGET_80387"  "*{  fp_pop_int (operands[0]);  RET;}")(define_insn "fix_truncdfqi2"  [(set (match_operand:QI 0 "general_operand" "=m,?*q")	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]  "TARGET_80387" "*{  fp_pop_int (operands[0]);  RET;}")(define_insn "fix_truncdfhi2"  [(set (match_operand:HI 0 "general_operand" "=m,?*r")	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]  "TARGET_80387"  "*{  fp_pop_int (operands[0]);  RET;}")(define_insn "fix_truncdfsi2"  [(set (match_operand:SI 0 "general_operand" "=m,?*r")	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]  "TARGET_80387"  "*{  fp_pop_int (operands[0]);  RET;}")*/;;- add instructions;;moved incl to above leal(define_insn "addsi3"  [(set (match_operand:SI 0 "general_operand" "=rm,r")	(plus:SI (match_operand:SI 1 "general_operand" "%0,0")		 (match_operand:SI 2 "general_operand" "ri,rm")))]  ""  "add%L0 %2,%0")(define_insn ""  [(set (match_operand:HI 0 "general_operand" "=g")	(plus:HI (match_operand:HI 1 "general_operand" "0")		 (const_int 1)))]  ""  "inc%W0 %0")(define_insn "addhi3"  [(set (match_operand:HI 0 "general_operand" "=rm,r")	(plus:HI (match_operand:HI 1 "general_operand" "%0,0")		 (match_operand:HI 2 "general_operand" "ri,rm")))]  ""  "add%W0 %2,%0")(define_insn ""  [(set (match_operand:QI 0 "general_operand" "=qm")	(plus:QI (match_operand:QI 1 "general_operand" "0")		 (const_int 1)))]  ""  "inc%B0 %0")(define_insn "addqi3"  [(set (match_operand:QI 0 "general_operand" "=m,q")	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")		 (match_operand:QI 2 "general_operand" "qn,qmn")))]  ""  "add%B0 %2,%0");;had "fmF,m"(define_insn "adddf3"  [(set (match_operand:DF 0 "general_operand" "=f,m,f")	(plus:DF (match_operand:DF 1 "general_operand" "%0,0,0")		 (match_operand:DF 2 "general_operand" "m,!f,!*r")))]  "TARGET_80387"  "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")(define_insn "addsf3"  [(set (match_operand:SF 0 "general_operand" "=f,m,f")	(plus:SF (match_operand:SF 1 "general_operand" "%0,0,0")		 (match_operand:SF 2 "general_operand" "m,!f,!*r")))]  "TARGET_80387"  "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)");;- subtract instructions;;moved decl above leal(define_insn "subsi3"  [(set (match_operand:SI 0 "general_operand" "=rm,r")	(minus:SI (match_operand:SI 1 "general_operand" "0,0")		  (match_operand:SI 2 "general_operand" "ri,rm")))]  ""  "sub%L0 %2,%0")(define_insn ""  [(set (match_operand:HI 0 "general_operand" "=g")	(minus:HI (match_operand:HI 1 "general_operand" "0")		  (const_int 1)))]  ""  "dec%W0 %0")(define_insn "subhi3"  [(set (match_operand:HI 0 "general_operand" "=rm,r")	(minus:HI (match_operand:HI 1 "general_operand" "0,0")		  (match_operand:HI 2 "general_operand" "ri,rm")))]  ""  "sub%W0 %2,%0")(define_insn ""  [(set (match_operand:QI 0 "general_operand" "=qm")	(minus:QI (match_operand:QI 1 "general_operand" "0")		  (const_int 1)))]  ""  "dec%B0 %0")(define_insn "subqi3"  [(set (match_operand:QI 0 "general_operand" "=m,q")	(minus:QI (match_operand:QI 1 "general_operand" "0,0")		  (match_operand:QI 2 "general_operand" "qn,qmn")))]  ""  "sub%B0 %2,%0")(define_insn "subdf3"  [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")	(minus:DF (match_operand:DF 1 "general_operand" "0,0,0,m")		  (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]  "TARGET_80387"  "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")(define_insn "subsf3"  [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")	(minus:SF (match_operand:SF 1 "general_operand" "0,0,0,m")		  (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]  "TARGET_80387"  "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)");;- multiply instructions;(define_insn "mulqi3";  [(set (match_operand:QI 0 "general_operand" "=a");	(mult:QI (match_operand:QI 1 "general_operand" "%0");		 (match_operand:QI 2 "general_operand" "qm")))];  "";  "mul%B0 %2,%0")(define_insn "mulhi3"  [(set (match_operand:HI 0 "general_operand" "=r,r")	(mult:SI (match_operand:HI 1 "general_operand" "%0,rm")		 (match_operand:HI 2 "general_operand" "g,i")))]  ""  "*{  if (GET_CODE (operands[1]) == REG      && REGNO (operands[1]) == REGNO (operands[0])      && (GET_CODE (operands[2]) == MEM	  || GET_CODE (operands[2]) == REG))    /* Assembler has weird restrictions.  */    return AS2 (imul%W0,%2,%0);  return AS3 (imul%W0,%2,%1,%0);}")(define_insn "mulsi3"  [(set (match_operand:SI 0 "general_operand" "=r,r")	(mult:SI (match_operand:SI 1 "general_operand" "%0,rm")		 (match_operand:SI 2 "general_operand" "g,i")))]  ""  "*{  if (GET_CODE (operands[1]) == REG      && REGNO (operands[1]) == REGNO (operands[0])      && (GET_CODE (operands[2]) == MEM	  || GET_CODE (operands[2]) == REG))    /* Assembler has weird restrictions.  */    return AS2 (imul%L0,%2,%0);  return AS3 (imul%L0,%2,%1,%0);}");; Turned off due to possible assembler bug.;(define_insn "umulqi3";  [(set (match_operand:QI 0 "general_operand" "=a");	(umult:QI (match_operand:QI 1 "general_operand" "%0");		  (match_operand:QI 2 "general_operand" "qm")))];  "";  "mul%B0 %2,%0");(define_insn "umulqihi3";  [(set (match_operand:HI 0 "general_operand" "=a");	(umult:HI (match_operand:QI 1 "general_operand" "%0");		  (match_operand:QI 2 "general_operand" "qm")))]