"TARGET_CE"  "fmovesd %1,%0")(define_insn "truncdfsf2"  [(set (match_operand:SF 0 "general_operand" "=f,m")	(float_truncate:SF	  (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]  "TARGET_CE"  "fmoveds %1,%0");; Conversion between fixed point and floating point.;; Note that among the fix-to-float insns;; the ones that start with SImode come first.;; That is so that an operand that is a CONST_INT;; (and therefore lacks a specific machine mode).;; will be recognized as SImode (which is always valid);; rather than as QImode or HImode.(define_insn "floatsisf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(float:SF (match_operand:SI 1 "nonimmediate_operand" "dm")))]  "TARGET_CE"  "fmovels %1,%0")(define_insn "floatsidf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(float:DF (match_operand:SI 1 "nonimmediate_operand" "dm")))]  "TARGET_CE"  "fmoveld %1,%0")(define_insn "floathisf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(float:SF (match_operand:HI 1 "nonimmediate_operand" "dm")))]  "TARGET_CE"  "fmovews %1,%0")(define_insn "floathidf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(float:DF (match_operand:HI 1 "nonimmediate_operand" "dm")))]  "TARGET_CE"  "fmovewd %1,%0")(define_insn "floatqisf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(float:SF (match_operand:QI 1 "nonimmediate_operand" "dm")))]  "TARGET_CE"  "fmovebs %1,%0")(define_insn "floatqidf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(float:DF (match_operand:QI 1 "nonimmediate_operand" "dm")))]  "TARGET_CE"  "fmovebd %1,%0");; Float-to-fix conversion insns.(define_insn "fix_truncsfqi2"  [(set (match_operand:QI 0 "general_operand" "=dm")	(fix:QI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]  "TARGET_CE"  "fmovesb %1,%0")(define_insn "fix_truncsfhi2"  [(set (match_operand:HI 0 "general_operand" "=dm")	(fix:HI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]  "TARGET_CE"  "fmovesw %1,%0")(define_insn "fix_truncsfsi2"  [(set (match_operand:SI 0 "general_operand" "=dm")	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]  "TARGET_CE"  "fmovesl %1,%0")(define_insn "fix_truncdfqi2"  [(set (match_operand:QI 0 "general_operand" "=dm")	(fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]  "TARGET_CE"  "fmovedb %1,%0")(define_insn "fix_truncdfhi2"  [(set (match_operand:HI 0 "general_operand" "=dm")	(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]  "TARGET_CE"  "fmovedw %1,%0")(define_insn "fix_truncdfsi2"  [(set (match_operand:SI 0 "general_operand" "=dm")	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]  "TARGET_CE"  "fmovedl %1,%0");; add instructions(define_insn "addsi3"  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,!a")	(plus:SI (match_operand:SI 1 "general_operand" "%0,0,a,rJK")		 (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK,a")))]  ""  "*{  if (! operands_match_p (operands[0], operands[1]))    {      if (!ADDRESS_REG_P (operands[1]))	{	  rtx tmp = operands[1];	  operands[1] = operands[2];	  operands[2] = tmp;	}      /* These insns can result from reloads to access	 stack slots over 64k from the frame pointer.  */      if (GET_CODE (operands[2]) == CONST_INT	  && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)        return \"mov%.l %2,%0\;add%.l %1,%0\";      if (GET_CODE (operands[2]) == REG)	return \"lea %1@[%2:L:B],%0\";      else	return \"lea %1@(%c2),%0\";    }  if (GET_CODE (operands[2]) == CONST_INT)    {      if (INTVAL (operands[2]) > 0	  && INTVAL (operands[2]) <= 8)	return (ADDRESS_REG_P (operands[0])		? \"addq%.w %2,%0\"		: \"addq%.l %2,%0\");      if (INTVAL (operands[2]) < 0	  && INTVAL (operands[2]) >= -8)        {	  operands[2] = gen_rtx (CONST_INT, VOIDmode,			         - INTVAL (operands[2]));	  return (ADDRESS_REG_P (operands[0])		  ? \"subq%.w %2,%0\"		  : \"subq%.l %2,%0\");	}      if (ADDRESS_REG_P (operands[0])	  && INTVAL (operands[2]) >= -0x8000	  && INTVAL (operands[2]) < 0x8000)	return \"add%.w %2,%0\";    }  return \"add%.l %2,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=a")	(plus:SI (match_operand:SI 1 "general_operand" "0")		 (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))]  ""  "add%.w %2,%0")(define_insn "addhi3"  [(set (match_operand:HI 0 "general_operand" "=m,r")	(plus:HI (match_operand:HI 1 "general_operand" "%0,0")		 (match_operand:HI 2 "general_operand" "dn,rmn")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT)    {      if (INTVAL (operands[2]) > 0	  && INTVAL (operands[2]) <= 8)	return \"addq%.w %2,%0\";    }  if (GET_CODE (operands[2]) == CONST_INT)    {      if (INTVAL (operands[2]) < 0	  && INTVAL (operands[2]) >= -8)	{	  operands[2] = gen_rtx (CONST_INT, VOIDmode,			         - INTVAL (operands[2]));	  return \"subq%.w %2,%0\";	}    }  return \"add%.w %2,%0\";}")(define_insn ""  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))	(plus:HI (match_dup 0)		 (match_operand:HI 1 "general_operand" "dn,rmn")))]  ""  "add%.w %1,%0")(define_insn "addqi3"  [(set (match_operand:QI 0 "general_operand" "=m,d")	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")		 (match_operand:QI 2 "general_operand" "dn,dmn")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT)    {      if (INTVAL (operands[2]) > 0	  && INTVAL (operands[2]) <= 8)	return \"addq%.b %2,%0\";    }  if (GET_CODE (operands[2]) == CONST_INT)    {      if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)       {	 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));	 return \"subq%.b %2,%0\";       }    }  return \"add%.b %2,%0\";}")(define_insn ""  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))	(plus:QI (match_dup 0)		 (match_operand:QI 1 "general_operand" "dn,dmn")))]  ""  "add%.b %1,%0")(define_insn "adddf3"  [(set (match_operand:DF 0 "register_operand" "=f")	(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%f")		 (match_operand:DF 2 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fadd%.d %2,%1,%0")(define_insn "addsf3"  [(set (match_operand:SF 0 "register_operand" "=f")	(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%f")		 (match_operand:SF 2 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fadd%.s %2,%1,%0");; subtract instructions(define_insn "subsi3"  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d")	(minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")		  (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]  ""  "*{  if (! operands_match_p (operands[0], operands[1]))    {      if (operands_match_p (operands[0], operands[2]))	{	  if (GET_CODE (operands[1]) == CONST_INT)	    {	      if (INTVAL (operands[1]) > 0		  && INTVAL (operands[1]) <= 8)		return \"subq%.l %1,%0\;neg%.l %0\";	    }	  return \"sub%.l %1,%0\;neg%.l %0\";	}      /* This case is matched by J, but negating -0x8000         in an lea would give an invalid displacement.	 So do this specially.  */      if (INTVAL (operands[2]) == -0x8000)	return \"mov%.l %1,%0\;sub%.l %2,%0\";      return \"lea %1@(%n2),%0\";    }  if (GET_CODE (operands[2]) == CONST_INT)    {      if (INTVAL (operands[2]) > 0	  && INTVAL (operands[2]) <= 8)	return \"subq%.l %2,%0\";      if (ADDRESS_REG_P (operands[0])	  && INTVAL (operands[2]) >= -0x8000	  && INTVAL (operands[2]) < 0x8000)	return \"sub%.w %2,%0\";    }  return \"sub%.l %2,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=a")	(minus:SI (match_operand:SI 1 "general_operand" "0")		  (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))]  ""  "sub%.w %2,%0")(define_insn "subhi3"  [(set (match_operand:HI 0 "general_operand" "=m,r")	(minus:HI (match_operand:HI 1 "general_operand" "0,0")		  (match_operand:HI 2 "general_operand" "dn,rmn")))]  ""  "sub%.w %2,%0")(define_insn ""  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))	(minus:HI (match_dup 0)		  (match_operand:HI 1 "general_operand" "dn,rmn")))]  ""  "sub%.w %1,%0")(define_insn "subqi3"  [(set (match_operand:QI 0 "general_operand" "=m,d")	(minus:QI (match_operand:QI 1 "general_operand" "0,0")		  (match_operand:QI 2 "general_operand" "dn,dmn")))]  ""  "sub%.b %2,%0")(define_insn ""  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))	(minus:QI (match_dup 0)		  (match_operand:QI 1 "general_operand" "dn,dmn")))]  ""  "sub%.b %1,%0")(define_insn "subdf3"  [(set (match_operand:DF 0 "register_operand" "=f,f")	(minus:DF (match_operand:DF 1 "nonimmediate_operand" "f,fm")		  (match_operand:DF 2 "nonimmediate_operand" "fm,f")))]  "TARGET_CE"  "*{  if (FP_REG_P (operands[1]))    return \"fsub%.d %2,%1,%0\";  return \"frsub%.d %1,%2,%0\";}")(define_insn "subsf3"  [(set (match_operand:SF 0 "register_operand" "=f,f")	(minus:SF (match_operand:SF 1 "nonimmediate_operand" "f,fm")		  (match_operand:SF 2 "nonimmediate_operand" "fm,f")))]  "TARGET_CE"  "*{  if (FP_REG_P (operands[1]))    return \"fsub%.s %2,%1,%0\";  return \"frsub%.s %1,%2,%0\";}");; multiply instructions(define_insn "mulhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(mult:HI (match_operand:HI 1 "general_operand" "%0")		 (match_operand:HI 2 "general_operand" "dmn")))]  ""  "muls %2,%0")(define_insn "mulhisi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(mult:SI (match_operand:HI 1 "general_operand" "%0")		 (match_operand:HI 2 "general_operand" "dmn")))]  ""  "muls %2,%0")(define_insn "mulsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(mult:SI (match_operand:SI 1 "general_operand" "%0")		 (match_operand:SI 2 "general_operand" "dmsK")))]  "TARGET_68020"  "muls%.l %2,%0")(define_insn "umulhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(umult:HI (match_operand:HI 1 "general_operand" "%0")		  (match_operand:HI 2 "general_operand" "dmn")))]  ""  "mulu %2,%0")(define_insn "umulhisi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(umult:SI (match_operand:HI 1 "general_operand" "%0")		  (match_operand:HI 2 "general_operand" "dmn")))]  ""  "mulu %2,%0")(define_insn "umulsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(umult:SI (match_operand:SI 1 "general_operand" "%0")		  (match_operand:SI 2 "general_operand" "dmsK")))]  "TARGET_68020"  "mulu%.l %2,%0")(define_insn "muldf3"  [(set (match_operand:DF 0 "register_operand" "=f")	(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%f")		 (match_operand:DF 2 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fmul%.d %2,%1,%0")(define_insn "mulsf3"  [(set (match_operand:SF 0 "register_operand" "=f")	(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%f")		 (match_operand:SF 2 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fmul%.s %2,%1,%0");; divide instructions(define_insn "divhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(div:HI (match_operand:HI 1 "general_operand" "0")		(match_operand:HI 2 "general_operand" "dmn")))]  ""  "extl %0\;divs %2,%0")(define_insn "divhisi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(div:HI (match_operand:SI 1 "general_operand" "0")		(match_operand:HI 2 "general_operand" "dmn")))]  ""  "divs %2,%0")(define_insn "divsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(div:SI (match_operand:SI 1 "general_operand" "0")		(match_operand:SI 2 "general_operand" "dmsK")))]  "TARGET_68020"  "divs%.l %2,%0,%0")(define_insn "udivhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(udiv:HI (match_operand:HI 1 "general_operand" "0")		 (match_operand:HI 2 "general_operand" "dmn")))]  ""  "and%.l %#0xFFFF,%0\;divu %2,%0")(define_insn "udivhisi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(udiv:HI (match_operand:SI 1 "general_operand" "0")		 (match_operand:HI 2 "general_operand" "dmn")))]  ""  "divu %2,%0")(define_insn "udivsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(udiv:SI (match_operand:SI 1 "general_operand" "0")		 (match_operand:SI 2 "general_operand" "dmsK")))]  "TARGET_68020"  "divu%.l %2,%0,%0")(define_insn "divdf3"  [(set (match_operand:DF 0 "register_operand" "=f,f")	(div:DF (match_operand:DF 1 "nonimmediate_operand" "f,fm")		(match_operand:DF 2 "nonimmediate_operand" "fm,f")))]  "TARGET_CE"  "*{  if (FP_REG_P (operands[1]))    return \"fdiv%.d %2,%1,%0\";