return \"frdiv%.d %1,%2,%0\";}")(define_insn "divsf3"  [(set (match_operand:SF 0 "register_operand" "=f,f")	(div:SF (match_operand:SF 1 "nonimmediate_operand" "f,fm")		(match_operand:SF 2 "nonimmediate_operand" "fm,f")))]  "TARGET_CE"  "*{  if (FP_REG_P (operands[1]))    return \"fdiv%.s %2,%1,%0\";  return \"frdiv%.s %1,%2,%0\";}");; Remainder instructions.(define_insn "modhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(mod:HI (match_operand:HI 1 "general_operand" "0")		(match_operand:HI 2 "general_operand" "dmn")))]  ""  "*{  /* The swap insn produces cc's that don't correspond to the result.  */  CC_STATUS_INIT;  return \"extl %0\;divs %2,%0\;swap %0\";}")(define_insn "modhisi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(mod:HI (match_operand:SI 1 "general_operand" "0")		(match_operand:HI 2 "general_operand" "dmn")))]  ""  "*{  /* The swap insn produces cc's that don't correspond to the result.  */  CC_STATUS_INIT;  return \"divs %2,%0\;swap %0\";}")(define_insn "umodhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(umod:HI (match_operand:HI 1 "general_operand" "0")		 (match_operand:HI 2 "general_operand" "dmn")))]  ""  "*{  /* The swap insn produces cc's that don't correspond to the result.  */  CC_STATUS_INIT;  return \"and%.l %#0xFFFF,%0\;divu %2,%0\;swap %0\";}")(define_insn "umodhisi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(umod:HI (match_operand:SI 1 "general_operand" "0")		 (match_operand:HI 2 "general_operand" "dmn")))]  ""  "*{  /* The swap insn produces cc's that don't correspond to the result.  */  CC_STATUS_INIT;  return \"divu %2,%0\;swap %0\";}")(define_insn "divmodsi4"  [(set (match_operand:SI 0 "general_operand" "=d")	(div:SI (match_operand:SI 1 "general_operand" "0")		(match_operand:SI 2 "general_operand" "dmsK")))   (set (match_operand:SI 3 "general_operand" "=d")	(mod:SI (match_dup 1) (match_dup 2)))]  "TARGET_68020"  "divs%.l %2,%0,%3")(define_insn "udivmodsi4"  [(set (match_operand:SI 0 "general_operand" "=d")	(udiv:SI (match_operand:SI 1 "general_operand" "0")		 (match_operand:SI 2 "general_operand" "dmsK")))   (set (match_operand:SI 3 "general_operand" "=d")	(umod:SI (match_dup 1) (match_dup 2)))]  "TARGET_68020"  "divu%.l %2,%0,%3");; logical-and instructions(define_insn "andsi3"  [(set (match_operand:SI 0 "general_operand" "=m,d")	(and:SI (match_operand:SI 1 "general_operand" "%0,0")		(match_operand:SI 2 "general_operand" "dKs,dmKs")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff      && (DATA_REG_P (operands[0])	  || offsettable_memref_p (operands[0])))    {       if (GET_CODE (operands[0]) != REG)        operands[0] = adj_offsettable_operand (operands[0], 2);      operands[2] = gen_rtx (CONST_INT, VOIDmode,			     INTVAL (operands[2]) & 0xffff);      /* Do not delete a following tstl %0 insn; that would be incorrect.  */      CC_STATUS_INIT;      if (operands[2] == const0_rtx)        return \"clr%.w %0\";      return \"and%.w %2,%0\";    }  return \"and%.l %2,%0\";}")(define_insn "andhi3"  [(set (match_operand:HI 0 "general_operand" "=m,d")	(and:HI (match_operand:HI 1 "general_operand" "%0,0")		(match_operand:HI 2 "general_operand" "dn,dmn")))]  ""  "and%.w %2,%0")(define_insn "andqi3"  [(set (match_operand:QI 0 "general_operand" "=m,d")	(and:QI (match_operand:QI 1 "general_operand" "%0,0")		(match_operand:QI 2 "general_operand" "dn,dmn")))]  ""  "and%.b %2,%0")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dm"))		(match_operand:SI 2 "general_operand" "0")))]  "GET_CODE (operands[2]) == CONST_INT   && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"  "and%.w %1,%0")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "dm"))		(match_operand:SI 2 "general_operand" "0")))]  "GET_CODE (operands[2]) == CONST_INT   && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"  "and%.b %1,%0");; inclusive-or instructions(define_insn "iorsi3"  [(set (match_operand:SI 0 "general_operand" "=m,d")	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")		(match_operand:SI 2 "general_operand" "dKs,dmKs")))]  ""  "*{  register int logval;  if (GET_CODE (operands[2]) == CONST_INT      && INTVAL (operands[2]) >> 16 == 0      && (DATA_REG_P (operands[0])	  || offsettable_memref_p (operands[0])))    {       if (GET_CODE (operands[0]) != REG)        operands[0] = adj_offsettable_operand (operands[0], 2);      /* Do not delete a following tstl %0 insn; that would be incorrect.  */      CC_STATUS_INIT;      return \"or%.w %2,%0\";    }  if (GET_CODE (operands[2]) == CONST_INT      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0      && (DATA_REG_P (operands[0])	  || offsettable_memref_p (operands[0])))    {       if (DATA_REG_P (operands[0]))	operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);      else        {	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));	  operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);	}      return \"bset %1,%0\";    }  return \"or%.l %2,%0\";}")(define_insn "iorhi3"  [(set (match_operand:HI 0 "general_operand" "=m,d")	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")		(match_operand:HI 2 "general_operand" "dn,dmn")))]  ""  "or%.w %2,%0")(define_insn "iorqi3"  [(set (match_operand:QI 0 "general_operand" "=m,d")	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")		(match_operand:QI 2 "general_operand" "dn,dmn")))]  ""  "or%.b %2,%0");; xor instructions(define_insn "xorsi3"  [(set (match_operand:SI 0 "general_operand" "=do,m")	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")		(match_operand:SI 2 "general_operand" "di,dKs")))]  ""  "*{  if (GET_CODE (operands[2]) == CONST_INT      && INTVAL (operands[2]) >> 16 == 0      && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))    {       if (! DATA_REG_P (operands[0]))	operands[0] = adj_offsettable_operand (operands[0], 2);      /* Do not delete a following tstl %0 insn; that would be incorrect.  */      CC_STATUS_INIT;      return \"eor%.w %2,%0\";    }  return \"eor%.l %2,%0\";}")(define_insn "xorhi3"  [(set (match_operand:HI 0 "general_operand" "=dm")	(xor:HI (match_operand:HI 1 "general_operand" "%0")		(match_operand:HI 2 "general_operand" "dn")))]  ""  "eor%.w %2,%0")(define_insn "xorqi3"  [(set (match_operand:QI 0 "general_operand" "=dm")	(xor:QI (match_operand:QI 1 "general_operand" "%0")		(match_operand:QI 2 "general_operand" "dn")))]  ""  "eor%.b %2,%0");; negation instructions(define_insn "negsi2"  [(set (match_operand:SI 0 "general_operand" "=dm")	(neg:SI (match_operand:SI 1 "general_operand" "0")))]  ""  "neg%.l %0")(define_insn "neghi2"  [(set (match_operand:HI 0 "general_operand" "=dm")	(neg:HI (match_operand:HI 1 "general_operand" "0")))]  ""  "neg%.w %0")(define_insn "negqi2"  [(set (match_operand:QI 0 "general_operand" "=dm")	(neg:QI (match_operand:QI 1 "general_operand" "0")))]  ""  "neg%.b %0")(define_insn "negsf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(neg:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fneg%.s %1,%0")(define_insn "negdf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fneg%.d %1,%0");; Absolute value instructions(define_insn "abssf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(abs:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fabs%.s %1,%0")(define_insn "absdf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fabs%.d %1,%0");; Square root instructions(define_insn "sqrtsf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fsqrt%.s %1,%0")(define_insn "sqrtdf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]  "TARGET_CE"  "fsqrt%.d %1,%0");; one complement instructions(define_insn "one_cmplsi2"  [(set (match_operand:SI 0 "general_operand" "=dm")	(not:SI (match_operand:SI 1 "general_operand" "0")))]  ""  "not%.l %0")(define_insn "one_cmplhi2"  [(set (match_operand:HI 0 "general_operand" "=dm")	(not:HI (match_operand:HI 1 "general_operand" "0")))]  ""  "not%.w %0")(define_insn "one_cmplqi2"  [(set (match_operand:QI 0 "general_operand" "=dm")	(not:QI (match_operand:QI 1 "general_operand" "0")))]  ""  "not%.b %0");; Optimized special case of shifting.;; Must precede the general case.(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")		     (const_int 24)))]  "GET_CODE (XEXP (operands[1], 0)) != POST_INC   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"  "*{  if (TARGET_68020)    return \"mov%.b %1,%0\;extb%.l %0\";  return \"mov%.b %1,%0\;ext%.w %0\;ext%.l %0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")		     (const_int 24)))]  "GET_CODE (XEXP (operands[1], 0)) != POST_INC   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"  "*{  if (reg_mentioned_p (operands[0], operands[1]))    return \"mov%.b %1,%0\;and%.l %#0xFF,%0\";  return \"clr%.l %0\;mov%.b %1,%0\";}")(define_insn ""  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")		       (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")				    (const_int 24))))]  "(GET_CODE (operands[0]) == CONST_INT    && (INTVAL (operands[0]) & ~0xff) == 0)"  "* cc_status.flags |= CC_REVERSED;  return \"cmp%.b %0,%1\";")(define_insn ""  [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")				    (const_int 24))		       (match_operand:QI 1 "general_operand" "i")))]  "(GET_CODE (operands[1]) == CONST_INT    && (INTVAL (operands[1]) & ~0xff) == 0)"  "*  return \"cmp%.b %1,%0\";")(define_insn ""  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")		       (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")				    (const_int 24))))]  "(GET_CODE (operands[0]) == CONST_INT    && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"  "* cc_status.flags |= CC_REVERSED;  return \"cmp%.b %0,%1\";")(define_insn ""  [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")				    (const_int 24))		       (match_operand:QI 1 "general_operand" "i")))]  "(GET_CODE (operands[1]) == CONST_INT    && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"  "*  return \"cmp%.b %1,%0\";");; arithmetic shift instructions;; We don't need the shift memory by 1 bit instruction(define_insn "ashlsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(ashift:SI (match_operand:SI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "dI")))]  ""  "asl%.l %2,%0")(define_insn "ashlhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(ashift:HI (match_operand:HI 1 "general_operand" "0")		   (match_operand:HI 2 "general_operand" "dI")))]  ""  "asl%.w %2,%0")(define_insn "ashlqi3"  [(set (match_operand:QI 0 "general_operand" "=d")	(ashift:QI (match_operand:QI 1 "general_operand" "0")		   (match_operand:QI 2 "general_operand" "dI")))]  ""  "asl%.b %2,%0")(define_insn "ashrsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")		     (match_operand:SI 2 "general_operand" "dI")))]  ""  "asr%.l %2,%0")(define_insn "ashrhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")		     (match_operand:HI 2 "general_operand" "dI")))]  ""  "asr%.w %2,%0")(define_insn "ashrqi3"  [(set (match_operand:QI 0 "general_operand" "=d")	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")		     (match_operand:QI 2 "general_operand" "dI")))]  ""  "asr%.b %2,%0");; logical shift instructions(define_insn "lshlsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(lshift:SI (match_operand:SI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "dI")))]  ""  "lsl%.l %2,%0")(define_insn "lshlhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(lshift:HI (match_operand:HI 1 "general_operand" "0")		   (match_operand:HI 2 "general_operand" "dI")))]  ""  "lsl%.w %2,%0")(define_insn "lshlqi3"  [(set (match_operand:QI 0 "general_operand" "=d")	(lshift:QI (match_operand:QI 1 "general_operand" "0")